nvdrv/devices/nvidia_ctrl_gpu : add IoctlCommands with their params (#524)
* add IoctlCommands with their params in nvidia_ctrl_gpu.h * add function related to the changes done previously * fix clang-format * delete trailing whitespace * correct mistake
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@ -26,6 +26,10 @@ u32 nvhost_ctrl_gpu::ioctl(Ioctl command, const std::vector<u8>& input, std::vec
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return ZCullGetInfo(input, output);
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case IoctlCommand::IocZbcSetTable:
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return ZBCSetTable(input, output);
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case IoctlCommand::IocZbcQueryTable:
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return ZBCQueryTable(input, output);
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case IoctlCommand::IocFlushL2:
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return FlushL2(input, output);
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}
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UNIMPLEMENTED_MSG("Unimplemented ioctl");
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return 0;
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@ -136,4 +140,22 @@ u32 nvhost_ctrl_gpu::ZBCSetTable(const std::vector<u8>& input, std::vector<u8>&
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return 0;
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}
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u32 nvhost_ctrl_gpu::ZBCQueryTable(const std::vector<u8>& input, std::vector<u8>& output) {
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NGLOG_WARNING(Service_NVDRV, "(STUBBED) called");
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IoctlZbcQueryTable params{};
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std::memcpy(¶ms, input.data(), input.size());
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// TODO : To implement properly
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std::memcpy(output.data(), ¶ms, output.size());
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return 0;
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}
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u32 nvhost_ctrl_gpu::FlushL2(const std::vector<u8>& input, std::vector<u8>& output) {
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NGLOG_WARNING(Service_NVDRV, "(STUBBED) called");
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IoctlFlushL2 params{};
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std::memcpy(¶ms, input.data(), input.size());
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// TODO : To implement properly
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std::memcpy(output.data(), ¶ms, output.size());
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return 0;
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}
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} // namespace Service::Nvidia::Devices
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@ -26,6 +26,18 @@ private:
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IocZcullGetCtxSizeCommand = 0x80044701,
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IocZcullGetInfo = 0x80284702,
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IocZbcSetTable = 0x402C4703,
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IocZbcQueryTable = 0xC0344704,
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IocFlushL2 = 0x40084707,
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IocInvalICache = 0x4008470D,
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IocSetMmudebugMode = 0x4008470E,
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IocSetSmDebugMode = 0x4010470F,
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IocWaitForPause = 0xC0084710,
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IocGetTcpExceptionEnStatus = 0x80084711,
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IocNumVsms = 0x80084712,
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IocVsmsMapping = 0xC0044713,
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IocGetErrorChannelUserData = 0xC008471B,
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IocGetGpuTime = 0xC010471C,
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IocGetCpuTimeCorrelationInfo = 0xC108471D,
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};
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struct IoctlGpuCharacteristics {
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@ -127,12 +139,31 @@ private:
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};
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static_assert(sizeof(IoctlZbcSetTable) == 44, "IoctlZbcSetTable is incorrect size");
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struct IoctlZbcQueryTable {
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u32_le color_ds[4];
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u32_le color_l2[4];
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u32_le depth;
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u32_le ref_cnt;
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u32_le format;
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u32_le type;
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u32_le index_size;
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};
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static_assert(sizeof(IoctlZbcQueryTable) == 52, "IoctlZbcQueryTable is incorrect size");
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struct IoctlFlushL2 {
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u32_le flush; // l2_flush | l2_invalidate << 1 | fb_flush << 2
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u32_le reserved;
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};
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static_assert(sizeof(IoctlFlushL2) == 8, "IoctlFlushL2 is incorrect size");
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u32 GetCharacteristics(const std::vector<u8>& input, std::vector<u8>& output);
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u32 GetTPCMasks(const std::vector<u8>& input, std::vector<u8>& output);
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u32 GetActiveSlotMask(const std::vector<u8>& input, std::vector<u8>& output);
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u32 ZCullGetCtxSize(const std::vector<u8>& input, std::vector<u8>& output);
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u32 ZCullGetInfo(const std::vector<u8>& input, std::vector<u8>& output);
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u32 ZBCSetTable(const std::vector<u8>& input, std::vector<u8>& output);
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u32 ZBCQueryTable(const std::vector<u8>& input, std::vector<u8>& output);
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u32 FlushL2(const std::vector<u8>& input, std::vector<u8>& output);
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};
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} // namespace Service::Nvidia::Devices
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