glasm: Initial implementation of phi nodes on GLASM
This commit is contained in:
parent
0f88fb5d72
commit
bf5e48ffe4
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@ -2,6 +2,7 @@
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// Licensed under GPLv2 or any later version
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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// Refer to the license.txt file included.
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#include <ranges>
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#include <string>
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#include <string>
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#include <tuple>
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#include <tuple>
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@ -9,6 +10,7 @@
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#include "shader_recompiler/backend/glasm/emit_context.h"
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#include "shader_recompiler/backend/glasm/emit_context.h"
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#include "shader_recompiler/backend/glasm/emit_glasm.h"
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#include "shader_recompiler/backend/glasm/emit_glasm.h"
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#include "shader_recompiler/backend/glasm/emit_glasm_instructions.h"
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#include "shader_recompiler/backend/glasm/emit_glasm_instructions.h"
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#include "shader_recompiler/frontend/ir/ir_emitter.h"
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#include "shader_recompiler/frontend/ir/program.h"
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#include "shader_recompiler/frontend/ir/program.h"
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#include "shader_recompiler/profile.h"
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#include "shader_recompiler/profile.h"
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@ -175,6 +177,34 @@ void EmitInst(EmitContext& ctx, IR::Inst* inst) {
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throw LogicError("Invalid opcode {}", inst->GetOpcode());
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throw LogicError("Invalid opcode {}", inst->GetOpcode());
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}
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}
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void Precolor(EmitContext& ctx, const IR::Program& program) {
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for (IR::Block* const block : program.blocks) {
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for (IR::Inst& phi : block->Instructions() | std::views::take_while(IR::IsPhi)) {
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switch (phi.Arg(0).Type()) {
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case IR::Type::U1:
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case IR::Type::U32:
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case IR::Type::F32:
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ctx.reg_alloc.Define(phi);
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break;
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case IR::Type::U64:
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case IR::Type::F64:
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ctx.reg_alloc.LongDefine(phi);
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break;
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default:
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throw NotImplementedException("Phi node type {}", phi.Type());
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}
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const size_t num_args{phi.NumArgs()};
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for (size_t i = 0; i < num_args; ++i) {
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IR::IREmitter{*phi.PhiBlock(i)}.PhiMove(phi, phi.Arg(i));
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}
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// Add reference to the phi node on the phi predecessor to avoid overwritting it
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for (size_t i = 0; i < num_args; ++i) {
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IR::IREmitter{*phi.PhiBlock(i)}.DummyReference(IR::Value{&phi});
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}
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}
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}
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}
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void EmitCode(EmitContext& ctx, const IR::Program& program) {
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void EmitCode(EmitContext& ctx, const IR::Program& program) {
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const auto eval{
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const auto eval{
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[&](const IR::U1& cond) { return ScalarS32{ctx.reg_alloc.Consume(IR::Value{cond})}; }};
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[&](const IR::U1& cond) { return ScalarS32{ctx.reg_alloc.Consume(IR::Value{cond})}; }};
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@ -186,7 +216,9 @@ void EmitCode(EmitContext& ctx, const IR::Program& program) {
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}
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}
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break;
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break;
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case IR::AbstractSyntaxNode::Type::If:
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case IR::AbstractSyntaxNode::Type::If:
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ctx.Add("MOV.S.CC RC,{};IF NE.x;", eval(node.if_node.cond));
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ctx.Add("MOV.S.CC RC,{};"
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"IF NE.x;",
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eval(node.if_node.cond));
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break;
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break;
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case IR::AbstractSyntaxNode::Type::EndIf:
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case IR::AbstractSyntaxNode::Type::EndIf:
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ctx.Add("ENDIF;");
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ctx.Add("ENDIF;");
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@ -195,10 +227,30 @@ void EmitCode(EmitContext& ctx, const IR::Program& program) {
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ctx.Add("REP;");
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ctx.Add("REP;");
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break;
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break;
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case IR::AbstractSyntaxNode::Type::Repeat:
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case IR::AbstractSyntaxNode::Type::Repeat:
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ctx.Add("MOV.S.CC RC,{};BRK NE.x;ENDREP;", eval(node.repeat.cond));
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if (node.repeat.cond.IsImmediate()) {
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if (node.repeat.cond.U1()) {
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ctx.Add("ENDREP;");
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} else {
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ctx.Add("BRK;"
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"ENDREP;");
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}
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} else {
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ctx.Add("MOV.S.CC RC,{};"
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"BRK (EQ.x);"
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"ENDREP;",
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eval(node.repeat.cond));
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}
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break;
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break;
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case IR::AbstractSyntaxNode::Type::Break:
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case IR::AbstractSyntaxNode::Type::Break:
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ctx.Add("MOV.S.CC RC,{};BRK NE.x;", eval(node.repeat.cond));
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if (node.break_node.cond.IsImmediate()) {
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if (node.break_node.cond.U1()) {
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ctx.Add("BRK;");
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}
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} else {
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ctx.Add("MOV.S.CC RC,{};"
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"BRK (NE.x);",
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eval(node.break_node.cond));
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}
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break;
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break;
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case IR::AbstractSyntaxNode::Type::Return:
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case IR::AbstractSyntaxNode::Type::Return:
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case IR::AbstractSyntaxNode::Type::Unreachable:
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case IR::AbstractSyntaxNode::Type::Unreachable:
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@ -233,6 +285,7 @@ void SetupOptions(std::string& header, Info info) {
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std::string EmitGLASM(const Profile&, IR::Program& program, Bindings&) {
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std::string EmitGLASM(const Profile&, IR::Program& program, Bindings&) {
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EmitContext ctx{program};
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EmitContext ctx{program};
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Precolor(ctx, program);
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EmitCode(ctx, program);
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EmitCode(ctx, program);
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std::string header = "!!NVcp5.0\n"
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std::string header = "!!NVcp5.0\n"
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"OPTION NV_internal;";
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"OPTION NV_internal;";
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@ -22,7 +22,8 @@ class EmitContext;
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void EmitPhi(EmitContext& ctx, IR::Inst& inst);
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void EmitPhi(EmitContext& ctx, IR::Inst& inst);
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void EmitVoid(EmitContext& ctx);
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void EmitVoid(EmitContext& ctx);
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void EmitIdentity(EmitContext& ctx, IR::Inst& inst, const IR::Value& value);
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void EmitIdentity(EmitContext& ctx, IR::Inst& inst, const IR::Value& value);
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void EmitBranchConditionRef(EmitContext&);
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void EmitDummyReference(EmitContext&);
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void EmitPhiMove(EmitContext& ctx, const IR::Value& phi, const IR::Value& value);
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void EmitJoin(EmitContext& ctx);
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void EmitJoin(EmitContext& ctx);
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void EmitDemoteToHelperInvocation(EmitContext& ctx);
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void EmitDemoteToHelperInvocation(EmitContext& ctx);
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void EmitBarrier(EmitContext& ctx);
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void EmitBarrier(EmitContext& ctx);
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@ -17,13 +17,32 @@ namespace Shader::Backend::GLASM {
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#define NotImplemented() throw NotImplementedException("GLASM instruction {}", __LINE__)
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#define NotImplemented() throw NotImplementedException("GLASM instruction {}", __LINE__)
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void EmitPhi(EmitContext& ctx, IR::Inst& inst) {
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void EmitPhi(EmitContext&, IR::Inst&) {}
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NotImplemented();
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}
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void EmitVoid(EmitContext&) {}
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void EmitVoid(EmitContext&) {}
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void EmitBranchConditionRef(EmitContext&) {}
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void EmitDummyReference(EmitContext&) {}
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void EmitPhiMove(EmitContext& ctx, const IR::Value& phi, const IR::Value& value) {
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if (phi == value) {
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return;
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}
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const Register phi_reg{ctx.reg_alloc.Consume(phi)};
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const Value eval_value{ctx.reg_alloc.Consume(value)};
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switch (phi.InstRecursive()->Arg(0).Type()) {
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case IR::Type::U1:
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case IR::Type::U32:
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case IR::Type::F32:
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ctx.Add("MOV.S {}.x,{};", phi_reg, ScalarS32{eval_value});
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break;
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case IR::Type::U64:
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case IR::Type::F64:
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ctx.Add("MOV.U64 {}.x,{};", phi_reg, ScalarRegister{eval_value});
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break;
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default:
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throw NotImplementedException("Phi node type {}", phi.Type());
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}
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}
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void EmitJoin(EmitContext& ctx) {
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void EmitJoin(EmitContext& ctx) {
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NotImplemented();
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NotImplemented();
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@ -468,7 +468,11 @@ Id EmitIdentity(EmitContext& ctx, const IR::Value& value) {
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return id;
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return id;
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}
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}
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void EmitBranchConditionRef(EmitContext&) {}
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void EmitDummyReference(EmitContext&) {}
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void EmitPhiMove(EmitContext&) {
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throw LogicError("Unreachable instruction");
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}
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void EmitGetZeroFromOp(EmitContext&) {
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void EmitGetZeroFromOp(EmitContext&) {
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throw LogicError("Unreachable instruction");
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throw LogicError("Unreachable instruction");
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@ -23,7 +23,8 @@ class EmitContext;
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Id EmitPhi(EmitContext& ctx, IR::Inst* inst);
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Id EmitPhi(EmitContext& ctx, IR::Inst* inst);
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void EmitVoid(EmitContext& ctx);
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void EmitVoid(EmitContext& ctx);
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Id EmitIdentity(EmitContext& ctx, const IR::Value& value);
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Id EmitIdentity(EmitContext& ctx, const IR::Value& value);
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void EmitBranchConditionRef(EmitContext&);
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void EmitDummyReference(EmitContext&);
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void EmitPhiMove(EmitContext&);
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void EmitJoin(EmitContext& ctx);
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void EmitJoin(EmitContext& ctx);
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void EmitDemoteToHelperInvocation(EmitContext& ctx);
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void EmitDemoteToHelperInvocation(EmitContext& ctx);
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void EmitBarrier(EmitContext& ctx);
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void EmitBarrier(EmitContext& ctx);
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return F64{Value{value}};
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return F64{Value{value}};
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}
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}
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void IREmitter::DummyReference(const Value& value) {
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Inst(Opcode::DummyReference, value);
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}
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void IREmitter::PhiMove(IR::Inst& phi, const Value& value) {
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Inst(Opcode::PhiMove, Value{&phi}, value);
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}
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void IREmitter::Prologue() {
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void IREmitter::Prologue() {
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Inst(Opcode::Prologue);
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Inst(Opcode::Prologue);
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}
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}
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@ -69,10 +77,6 @@ void IREmitter::Epilogue() {
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Inst(Opcode::Epilogue);
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Inst(Opcode::Epilogue);
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}
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}
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void IREmitter::BranchConditionRef(const U1& cond) {
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Inst(Opcode::BranchConditionRef, cond);
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}
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void IREmitter::DemoteToHelperInvocation() {
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void IREmitter::DemoteToHelperInvocation() {
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Inst(Opcode::DemoteToHelperInvocation);
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Inst(Opcode::DemoteToHelperInvocation);
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}
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}
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@ -106,6 +110,9 @@ void IREmitter::SetReg(IR::Reg reg, const U32& value) {
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}
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}
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U1 IREmitter::GetPred(IR::Pred pred, bool is_negated) {
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U1 IREmitter::GetPred(IR::Pred pred, bool is_negated) {
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if (pred == Pred::PT) {
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return Imm1(!is_negated);
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}
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const U1 value{Inst<U1>(Opcode::GetPred, pred)};
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const U1 value{Inst<U1>(Opcode::GetPred, pred)};
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if (is_negated) {
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if (is_negated) {
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return Inst<U1>(Opcode::LogicalNot, value);
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return Inst<U1>(Opcode::LogicalNot, value);
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@ -264,6 +271,9 @@ static U1 GetFlowTest(IREmitter& ir, FlowTest flow_test) {
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U1 IREmitter::Condition(IR::Condition cond) {
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U1 IREmitter::Condition(IR::Condition cond) {
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const FlowTest flow_test{cond.GetFlowTest()};
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const FlowTest flow_test{cond.GetFlowTest()};
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const auto [pred, is_negated]{cond.GetPred()};
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const auto [pred, is_negated]{cond.GetPred()};
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if (flow_test == FlowTest::T) {
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return GetPred(pred, is_negated);
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}
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return LogicalAnd(GetPred(pred, is_negated), GetFlowTest(*this, flow_test));
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return LogicalAnd(GetPred(pred, is_negated), GetFlowTest(*this, flow_test));
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}
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}
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[[nodiscard]] U64 Imm64(s64 value) const;
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[[nodiscard]] U64 Imm64(s64 value) const;
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[[nodiscard]] F64 Imm64(f64 value) const;
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[[nodiscard]] F64 Imm64(f64 value) const;
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void DummyReference(const Value& value);
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void PhiMove(IR::Inst& phi, const Value& value);
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void Prologue();
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void Prologue();
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void Epilogue();
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void Epilogue();
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void BranchConditionRef(const U1& cond);
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void DemoteToHelperInvocation();
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void DemoteToHelperInvocation();
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void EmitVertex(const U32& stream);
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void EmitVertex(const U32& stream);
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void EndPrimitive(const U32& stream);
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void EndPrimitive(const U32& stream);
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@ -56,9 +56,10 @@ Inst::~Inst() {
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bool Inst::MayHaveSideEffects() const noexcept {
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bool Inst::MayHaveSideEffects() const noexcept {
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switch (op) {
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switch (op) {
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case Opcode::DummyReference:
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case Opcode::PhiMove:
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case Opcode::Prologue:
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case Opcode::Prologue:
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case Opcode::Epilogue:
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case Opcode::Epilogue:
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case Opcode::BranchConditionRef:
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case Opcode::Join:
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case Opcode::Join:
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case Opcode::DemoteToHelperInvocation:
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case Opcode::DemoteToHelperInvocation:
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case Opcode::Barrier:
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case Opcode::Barrier:
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@ -6,11 +6,12 @@
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OPCODE(Phi, Opaque, )
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OPCODE(Phi, Opaque, )
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OPCODE(Identity, Opaque, Opaque, )
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OPCODE(Identity, Opaque, Opaque, )
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OPCODE(Void, Void, )
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OPCODE(Void, Void, )
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OPCODE(DummyReference, Void, Opaque, )
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OPCODE(PhiMove, Void, Opaque, Opaque, )
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// Special operations
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// Special operations
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OPCODE(Prologue, Void, )
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OPCODE(Prologue, Void, )
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OPCODE(Epilogue, Void, )
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OPCODE(Epilogue, Void, )
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OPCODE(BranchConditionRef, Void, U1, )
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OPCODE(Join, Void, )
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OPCODE(Join, Void, )
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OPCODE(DemoteToHelperInvocation, Void, )
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OPCODE(DemoteToHelperInvocation, Void, )
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OPCODE(EmitVertex, Void, U32, )
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OPCODE(EmitVertex, Void, U32, )
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@ -391,4 +391,8 @@ inline f64 Value::F64() const {
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return imm_f64;
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return imm_f64;
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}
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}
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[[nodiscard]] inline bool IsPhi(const Inst& inst) {
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return inst.GetOpcode() == Opcode::Phi;
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}
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} // namespace Shader::IR
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} // namespace Shader::IR
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@ -704,7 +704,7 @@ private:
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// Implement if header block
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// Implement if header block
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IR::IREmitter ir{*current_block};
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IR::IREmitter ir{*current_block};
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const IR::U1 cond{VisitExpr(ir, *stmt.cond)};
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const IR::U1 cond{VisitExpr(ir, *stmt.cond)};
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ir.BranchConditionRef(cond);
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ir.DummyReference(cond);
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const size_t if_node_index{syntax_list.size()};
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const size_t if_node_index{syntax_list.size()};
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syntax_list.emplace_back();
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syntax_list.emplace_back();
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@ -755,7 +755,7 @@ private:
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// The continue block is located at the end of the loop
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// The continue block is located at the end of the loop
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IR::IREmitter ir{*continue_block};
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IR::IREmitter ir{*continue_block};
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const IR::U1 cond{VisitExpr(ir, *stmt.cond)};
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const IR::U1 cond{VisitExpr(ir, *stmt.cond)};
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ir.BranchConditionRef(cond);
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ir.DummyReference(cond);
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IR::Block* const body_block{syntax_list.at(body_block_index).block};
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IR::Block* const body_block{syntax_list.at(body_block_index).block};
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loop_header_block->AddBranch(body_block);
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loop_header_block->AddBranch(body_block);
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@ -792,7 +792,7 @@ private:
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IR::IREmitter ir{*current_block};
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IR::IREmitter ir{*current_block};
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const IR::U1 cond{VisitExpr(ir, *stmt.cond)};
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const IR::U1 cond{VisitExpr(ir, *stmt.cond)};
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ir.BranchConditionRef(cond);
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ir.DummyReference(cond);
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current_block->AddBranch(break_block);
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current_block->AddBranch(break_block);
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current_block->AddBranch(skip_block);
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current_block->AddBranch(skip_block);
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current_block = skip_block;
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current_block = skip_block;
|
||||||
|
|
|
@ -138,10 +138,6 @@ IR::Opcode UndefOpcode(IndirectBranchVariable) noexcept {
|
||||||
return IR::Opcode::UndefU32;
|
return IR::Opcode::UndefU32;
|
||||||
}
|
}
|
||||||
|
|
||||||
[[nodiscard]] bool IsPhi(const IR::Inst& inst) noexcept {
|
|
||||||
return inst.GetOpcode() == IR::Opcode::Phi;
|
|
||||||
}
|
|
||||||
|
|
||||||
enum class Status {
|
enum class Status {
|
||||||
Start,
|
Start,
|
||||||
SetValue,
|
SetValue,
|
||||||
|
@ -283,7 +279,7 @@ private:
|
||||||
list.erase(IR::Block::InstructionList::s_iterator_to(phi));
|
list.erase(IR::Block::InstructionList::s_iterator_to(phi));
|
||||||
|
|
||||||
// Find the first non-phi instruction and use it as an insertion point
|
// Find the first non-phi instruction and use it as an insertion point
|
||||||
IR::Block::iterator reinsert_point{std::ranges::find_if_not(list, IsPhi)};
|
IR::Block::iterator reinsert_point{std::ranges::find_if_not(list, IR::IsPhi)};
|
||||||
if (same.IsEmpty()) {
|
if (same.IsEmpty()) {
|
||||||
// The phi is unreachable or in the start block
|
// The phi is unreachable or in the start block
|
||||||
// Insert an undefined instruction and make it the phi node replacement
|
// Insert an undefined instruction and make it the phi node replacement
|
||||||
|
|
Reference in New Issue