shader: Support SSA loops on IR
This commit is contained in:
parent
8af9297f09
commit
cbfb7d182a
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@ -32,6 +32,8 @@ add_executable(shader_recompiler
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frontend/ir/opcodes.cpp
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frontend/ir/opcodes.h
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frontend/ir/opcodes.inc
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frontend/ir/post_order.cpp
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frontend/ir/post_order.h
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frontend/ir/pred.h
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frontend/ir/program.cpp
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frontend/ir/program.h
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@ -159,10 +159,10 @@ private:
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Id EmitWorkgroupId(EmitContext& ctx);
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Id EmitLocalInvocationId(EmitContext& ctx);
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Id EmitUndefU1(EmitContext& ctx);
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void EmitUndefU8(EmitContext& ctx);
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void EmitUndefU16(EmitContext& ctx);
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void EmitUndefU32(EmitContext& ctx);
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void EmitUndefU64(EmitContext& ctx);
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Id EmitUndefU8(EmitContext& ctx);
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Id EmitUndefU16(EmitContext& ctx);
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Id EmitUndefU32(EmitContext& ctx);
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Id EmitUndefU64(EmitContext& ctx);
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void EmitLoadGlobalU8(EmitContext& ctx);
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void EmitLoadGlobalS8(EmitContext& ctx);
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void EmitLoadGlobalU16(EmitContext& ctx);
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@ -297,12 +297,12 @@ private:
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void EmitBitFieldInsert(EmitContext& ctx);
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void EmitBitFieldSExtract(EmitContext& ctx);
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Id EmitBitFieldUExtract(EmitContext& ctx, Id base, Id offset, Id count);
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void EmitSLessThan(EmitContext& ctx);
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Id EmitSLessThan(EmitContext& ctx, Id lhs, Id rhs);
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void EmitULessThan(EmitContext& ctx);
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void EmitIEqual(EmitContext& ctx);
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void EmitSLessThanEqual(EmitContext& ctx);
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void EmitULessThanEqual(EmitContext& ctx);
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void EmitSGreaterThan(EmitContext& ctx);
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Id EmitSGreaterThan(EmitContext& ctx, Id lhs, Id rhs);
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void EmitUGreaterThan(EmitContext& ctx);
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void EmitINotEqual(EmitContext& ctx);
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void EmitSGreaterThanEqual(EmitContext& ctx);
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@ -73,8 +73,8 @@ Id EmitSPIRV::EmitBitFieldUExtract(EmitContext& ctx, Id base, Id offset, Id coun
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return ctx.OpBitFieldUExtract(ctx.u32[1], base, offset, count);
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}
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void EmitSPIRV::EmitSLessThan(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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Id EmitSPIRV::EmitSLessThan(EmitContext& ctx, Id lhs, Id rhs) {
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return ctx.OpSLessThan(ctx.u1, lhs, rhs);
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}
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void EmitSPIRV::EmitULessThan(EmitContext&) {
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@ -93,8 +93,8 @@ void EmitSPIRV::EmitULessThanEqual(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitSPIRV::EmitSGreaterThan(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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Id EmitSPIRV::EmitSGreaterThan(EmitContext& ctx, Id lhs, Id rhs) {
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return ctx.OpSGreaterThan(ctx.u1, lhs, rhs);
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}
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void EmitSPIRV::EmitUGreaterThan(EmitContext&) {
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@ -10,19 +10,19 @@ Id EmitSPIRV::EmitUndefU1(EmitContext& ctx) {
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return ctx.OpUndef(ctx.u1);
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}
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void EmitSPIRV::EmitUndefU8(EmitContext&) {
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Id EmitSPIRV::EmitUndefU8(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitSPIRV::EmitUndefU16(EmitContext&) {
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Id EmitSPIRV::EmitUndefU16(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitSPIRV::EmitUndefU32(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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Id EmitSPIRV::EmitUndefU32(EmitContext& ctx) {
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return ctx.OpUndef(ctx.u32[1]);
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}
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void EmitSPIRV::EmitUndefU64(EmitContext&) {
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Id EmitSPIRV::EmitUndefU64(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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@ -12,6 +12,7 @@ namespace Shader::IR {
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struct Function {
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BlockList blocks;
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BlockList post_order_blocks;
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};
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} // namespace Shader::IR
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@ -0,0 +1,48 @@
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// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <boost/container/flat_set.hpp>
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#include <boost/container/small_vector.hpp>
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#include "shader_recompiler/frontend/ir/basic_block.h"
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#include "shader_recompiler/frontend/ir/post_order.h"
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namespace Shader::IR {
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BlockList PostOrder(const BlockList& blocks) {
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boost::container::small_vector<Block*, 16> block_stack;
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boost::container::flat_set<Block*> visited;
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BlockList post_order_blocks;
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post_order_blocks.reserve(blocks.size());
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Block* const first_block{blocks.front()};
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visited.insert(first_block);
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block_stack.push_back(first_block);
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const auto visit_branch = [&](Block* block, Block* branch) {
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if (!branch) {
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return false;
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}
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if (!visited.insert(branch).second) {
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return false;
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}
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// Calling push_back twice is faster than insert on msvc
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block_stack.push_back(block);
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block_stack.push_back(branch);
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return true;
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};
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while (!block_stack.empty()) {
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Block* const block{block_stack.back()};
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block_stack.pop_back();
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if (!visit_branch(block, block->TrueBranch()) &&
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!visit_branch(block, block->FalseBranch())) {
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post_order_blocks.push_back(block);
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}
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}
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return post_order_blocks;
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}
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} // namespace Shader::IR
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@ -0,0 +1,13 @@
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// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#pragma once
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#include "shader_recompiler/frontend/ir/basic_block.h"
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namespace Shader::IR {
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BlockList PostOrder(const BlockList& blocks);
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} // namespace Shader::IR
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@ -7,6 +7,7 @@
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#include <vector>
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#include "shader_recompiler/frontend/ir/basic_block.h"
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#include "shader_recompiler/frontend/ir/post_order.h"
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#include "shader_recompiler/frontend/ir/structured_control_flow.h"
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#include "shader_recompiler/frontend/maxwell/program.h"
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#include "shader_recompiler/frontend/maxwell/translate/translate.h"
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@ -56,11 +57,14 @@ IR::Program TranslateProgram(ObjectPool<IR::Inst>& inst_pool, ObjectPool<IR::Blo
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}
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fmt::print(stdout, "No optimizations: {}", IR::DumpProgram(program));
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std::ranges::for_each(functions, Optimization::SsaRewritePass);
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for (IR::Function& function : functions) {
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Optimization::Invoke(Optimization::GlobalMemoryToStorageBufferPass, function);
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Optimization::Invoke(Optimization::ConstantPropagationPass, function);
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Optimization::Invoke(Optimization::DeadCodeEliminationPass, function);
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function.post_order_blocks = PostOrder(function.blocks);
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Optimization::SsaRewritePass(function.post_order_blocks);
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}
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for (IR::Function& function : functions) {
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Optimization::PostOrderInvoke(Optimization::GlobalMemoryToStorageBufferPass, function);
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Optimization::PostOrderInvoke(Optimization::ConstantPropagationPass, function);
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Optimization::PostOrderInvoke(Optimization::DeadCodeEliminationPass, function);
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Optimization::IdentityRemovalPass(function);
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Optimization::VerificationPass(function);
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}
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@ -13,7 +13,7 @@ namespace Shader::Optimization {
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void DeadCodeEliminationPass(IR::Block& block) {
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// We iterate over the instructions in reverse order.
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// This is because removing an instruction reduces the number of uses for earlier instructions.
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for (IR::Inst& inst : std::views::reverse(block)) {
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for (IR::Inst& inst : block | std::views::reverse) {
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if (!inst.HasUses() && !inst.MayHaveSideEffects()) {
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inst.Invalidate();
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}
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@ -4,14 +4,16 @@
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#pragma once
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#include <span>
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#include "shader_recompiler/frontend/ir/basic_block.h"
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#include "shader_recompiler/frontend/ir/function.h"
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namespace Shader::Optimization {
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template <typename Func>
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void Invoke(Func&& func, IR::Function& function) {
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for (const auto& block : function.blocks) {
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void PostOrderInvoke(Func&& func, IR::Function& function) {
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for (const auto& block : function.post_order_blocks) {
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func(*block);
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}
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}
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@ -20,7 +22,7 @@ void ConstantPropagationPass(IR::Block& block);
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void DeadCodeEliminationPass(IR::Block& block);
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void GlobalMemoryToStorageBufferPass(IR::Block& block);
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void IdentityRemovalPass(IR::Function& function);
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void SsaRewritePass(IR::Function& function);
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void SsaRewritePass(std::span<IR::Block* const> post_order_blocks);
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void VerificationPass(const IR::Function& function);
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} // namespace Shader::Optimization
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@ -14,7 +14,13 @@
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// https://link.springer.com/chapter/10.1007/978-3-642-37051-9_6
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//
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#include <ranges>
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#include <span>
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#include <variant>
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#include <vector>
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#include <boost/container/flat_map.hpp>
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#include <boost/container/flat_set.hpp>
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#include "shader_recompiler/frontend/ir/basic_block.h"
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#include "shader_recompiler/frontend/ir/function.h"
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@ -26,9 +32,9 @@
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namespace Shader::Optimization {
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namespace {
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using ValueMap = boost::container::flat_map<IR::Block*, IR::Value, std::less<IR::Block*>>;
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struct FlagTag {};
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struct FlagTag {
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auto operator<=>(const FlagTag&) const noexcept = default;
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};
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struct ZeroFlagTag : FlagTag {};
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struct SignFlagTag : FlagTag {};
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struct CarryFlagTag : FlagTag {};
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@ -38,9 +44,15 @@ struct GotoVariable : FlagTag {
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GotoVariable() = default;
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explicit GotoVariable(u32 index_) : index{index_} {}
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auto operator<=>(const GotoVariable&) const noexcept = default;
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u32 index;
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};
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using Variant = std::variant<IR::Reg, IR::Pred, ZeroFlagTag, SignFlagTag, CarryFlagTag,
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OverflowFlagTag, GotoVariable>;
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using ValueMap = boost::container::flat_map<IR::Block*, IR::Value, std::less<IR::Block*>>;
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struct DefTable {
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[[nodiscard]] ValueMap& operator[](IR::Reg variable) noexcept {
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return regs[IR::RegIndex(variable)];
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@ -102,19 +114,35 @@ public:
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}
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IR::Value ReadVariable(auto variable, IR::Block* block) {
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auto& def{current_def[variable]};
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const ValueMap& def{current_def[variable]};
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if (const auto it{def.find(block)}; it != def.end()) {
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return it->second;
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}
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return ReadVariableRecursive(variable, block);
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}
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void SealBlock(IR::Block* block) {
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const auto it{incomplete_phis.find(block)};
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if (it != incomplete_phis.end()) {
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for (auto& [variant, phi] : it->second) {
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std::visit([&](auto& variable) { AddPhiOperands(variable, *phi, block); }, variant);
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}
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}
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sealed_blocks.insert(block);
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}
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private:
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IR::Value ReadVariableRecursive(auto variable, IR::Block* block) {
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IR::Value val;
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if (const std::span preds{block->ImmediatePredecessors()}; preds.size() == 1) {
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if (!sealed_blocks.contains(block)) {
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// Incomplete CFG
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IR::Inst* phi{&*block->PrependNewInst(block->begin(), IR::Opcode::Phi)};
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incomplete_phis[block].insert_or_assign(variable, phi);
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val = IR::Value{&*phi};
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} else if (const std::span imm_preds{block->ImmediatePredecessors()};
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imm_preds.size() == 1) {
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// Optimize the common case of one predecessor: no phi needed
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val = ReadVariable(variable, preds.front());
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val = ReadVariable(variable, imm_preds.front());
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} else {
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// Break potential cycles with operandless phi
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IR::Inst& phi_inst{*block->PrependNewInst(block->begin(), IR::Opcode::Phi)};
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}
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IR::Value AddPhiOperands(auto variable, IR::Inst& phi, IR::Block* block) {
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for (IR::Block* const pred : block->ImmediatePredecessors()) {
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phi.AddPhiOperand(pred, ReadVariable(variable, pred));
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for (IR::Block* const imm_pred : block->ImmediatePredecessors()) {
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phi.AddPhiOperand(imm_pred, ReadVariable(variable, imm_pred));
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}
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return TryRemoveTrivialPhi(phi, block, UndefOpcode(variable));
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}
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@ -159,6 +187,9 @@ private:
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return same;
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}
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boost::container::flat_set<IR::Block*> sealed_blocks;
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boost::container::flat_map<IR::Block*, boost::container::flat_map<Variant, IR::Inst*>>
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incomplete_phis;
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DefTable current_def;
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};
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@ -218,14 +249,19 @@ void VisitInst(Pass& pass, IR::Block* block, IR::Inst& inst) {
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break;
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}
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}
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void VisitBlock(Pass& pass, IR::Block* block) {
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for (IR::Inst& inst : block->Instructions()) {
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VisitInst(pass, block, inst);
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}
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pass.SealBlock(block);
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}
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} // Anonymous namespace
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void SsaRewritePass(IR::Function& function) {
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void SsaRewritePass(std::span<IR::Block* const> post_order_blocks) {
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Pass pass;
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for (IR::Block* const block : function.blocks) {
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for (IR::Inst& inst : block->Instructions()) {
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VisitInst(pass, block, inst);
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}
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for (IR::Block* const block : post_order_blocks | std::views::reverse) {
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VisitBlock(pass, block);
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}
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}
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@ -69,14 +69,12 @@ int main() {
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// FileEnvironment env{"D:\\Shaders\\Database\\Oninaki\\CS8F146B41DB6BD826.bin"};
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FileEnvironment env{"D:\\Shaders\\shader.bin"};
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for (int i = 0; i < 1; ++i) {
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block_pool->ReleaseContents();
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inst_pool->ReleaseContents();
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flow_block_pool->ReleaseContents();
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Flow::CFG cfg{env, *flow_block_pool, 0};
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fmt::print(stdout, "{}\n", cfg.Dot());
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IR::Program program{TranslateProgram(*inst_pool, *block_pool, env, cfg)};
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fmt::print(stdout, "{}\n", IR::DumpProgram(program));
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Backend::SPIRV::EmitSPIRV spirv{program};
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}
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block_pool->ReleaseContents();
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inst_pool->ReleaseContents();
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flow_block_pool->ReleaseContents();
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Flow::CFG cfg{env, *flow_block_pool, 0};
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fmt::print(stdout, "{}\n", cfg.Dot());
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IR::Program program{TranslateProgram(*inst_pool, *block_pool, env, cfg)};
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fmt::print(stdout, "{}\n", IR::DumpProgram(program));
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// Backend::SPIRV::EmitSPIRV spirv{program};
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}
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