shader_ir: Unify blocks in decompiled shaders.
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926b80102f
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d5533b440c
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@ -191,10 +191,12 @@ public:
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// TODO(Subv): Figure out the actual depth of the flow stack, for now it seems
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// unlikely that shaders will use 20 nested SSYs and PBKs.
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constexpr u32 FLOW_STACK_SIZE = 20;
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for (const auto stack : std::array{MetaStackClass::Ssy, MetaStackClass::Pbk}) {
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code.AddLine("uint {}[{}];", FlowStackName(stack), FLOW_STACK_SIZE);
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code.AddLine("uint {} = 0u;", FlowStackTopName(stack));
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if (!ir.IsFlowStackDisabled()) {
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constexpr u32 FLOW_STACK_SIZE = 20;
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for (const auto stack : std::array{MetaStackClass::Ssy, MetaStackClass::Pbk}) {
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code.AddLine("uint {}[{}];", FlowStackName(stack), FLOW_STACK_SIZE);
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code.AddLine("uint {} = 0u;", FlowStackTopName(stack));
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}
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}
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code.AddLine("while (true) {{");
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@ -1,5 +1,6 @@
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#include <list>
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#include <map>
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#include <unordered_map>
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#include <unordered_set>
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#include <vector>
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@ -104,28 +105,6 @@ struct BlockInfo {
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}
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};
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struct Stamp {
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Stamp() = default;
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Stamp(u32 address, u32 target) : address{address}, target{target} {}
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u32 address{};
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u32 target{};
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bool operator==(const Stamp& sb) const {
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return std::tie(address, target) == std::tie(sb.address, sb.target);
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}
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bool operator<(const Stamp& sb) const {
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return address < sb.address;
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}
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bool operator>(const Stamp& sb) const {
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return address > sb.address;
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}
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bool operator<=(const Stamp& sb) const {
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return address <= sb.address;
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}
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bool operator>=(const Stamp& sb) const {
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return address >= sb.address;
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}
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};
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struct CFGRebuildState {
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explicit CFGRebuildState(const ProgramCode& program_code, const std::size_t program_size)
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: program_code{program_code}, program_size{program_size} {
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@ -144,8 +123,8 @@ struct CFGRebuildState {
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std::list<Query> queries{};
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std::unordered_map<u32, u32> registered{};
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std::unordered_set<u32> labels{};
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std::set<Stamp> ssy_labels;
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std::set<Stamp> pbk_labels;
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std::map<u32, u32> ssy_labels;
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std::map<u32, u32> pbk_labels;
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std::unordered_map<u32, BlockStack> stacks{};
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const ProgramCode& program_code;
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const std::size_t program_size;
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@ -393,7 +372,7 @@ bool TryInspectAddress(CFGRebuildState& state) {
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}
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case BlockCollision::Inside: {
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// This case is the tricky one:
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// We need to Split the block in 2 sepprate blocks
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// We need to Split the block in 2 sepparate blocks
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auto it = search_result.second;
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block_info = CreateBlockInfo(state, address, it->end);
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it->end = address - 1;
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@ -428,13 +407,11 @@ bool TryInspectAddress(CFGRebuildState& state) {
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}
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bool TryQuery(CFGRebuildState& state) {
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auto gather_labels = ([](ControlStack& cc, std::set<Stamp> labels, BlockInfo& block) {
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Stamp start{block.start, 0};
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Stamp end{block.end, 0};
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auto gather_start = labels.lower_bound(start);
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auto gather_end = labels.upper_bound(end);
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auto gather_labels = ([](ControlStack& cc, std::map<u32, u32>& labels, BlockInfo& block) {
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auto gather_start = labels.lower_bound(block.start);
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auto gather_end = labels.upper_bound(block.end);
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while (gather_start != gather_end) {
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cc.Push(gather_start->target);
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cc.Push(gather_start->second);
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gather_start++;
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}
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});
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@ -444,9 +421,13 @@ bool TryQuery(CFGRebuildState& state) {
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Query& q = state.queries.front();
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u32 block_index = state.registered[q.address];
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BlockInfo& block = state.block_info[block_index];
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// If the block is visted, check if the stacks match, else gather the ssy/pbk
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// labels into the current stack and look if the branch at the end of the block
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// consumes a label. Schedule new queries accordingly
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if (block.visited) {
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BlockStack& stack = state.stacks[q.address];
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bool all_okay = q.ssy_stack.Compare(stack.ssy_stack) && q.pbk_stack.Compare(stack.pbk_stack);
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bool all_okay = (stack.ssy_stack.Size() == 0 || q.ssy_stack.Compare(stack.ssy_stack)) &&
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(stack.pbk_stack.Size() == 0 || q.pbk_stack.Compare(stack.pbk_stack));
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state.queries.pop_front();
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return all_okay;
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}
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@ -523,8 +504,10 @@ bool ScanFlow(const ProgramCode& program_code, u32 program_size, u32 start_addre
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result_out.blocks.push_back(new_block);
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}
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if (result_out.decompilable) {
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result_out.labels = std::move(state.labels);
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return true;
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}
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// If it's not decompilable, merge the unlabelled blocks together
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auto back = result_out.blocks.begin();
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auto next = std::next(back);
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while (next != result_out.blocks.end()) {
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@ -3,7 +3,7 @@
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#include <cstring>
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#include <list>
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#include <optional>
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#include <vector>
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#include <unordered_set>
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#include "video_core/engines/shader_bytecode.h"
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#include "video_core/shader/shader_ir.h"
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@ -48,6 +48,7 @@ struct ShaderCharacteristics {
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bool decompilable{};
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u32 start;
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u32 end;
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std::unordered_set<u32> labels{};
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};
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bool ScanFlow(const ProgramCode& program_code, u32 program_size, u32 start_address,
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@ -38,32 +38,47 @@ constexpr bool IsSchedInstruction(u32 offset, u32 main_offset) {
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void ShaderIR::Decode() {
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std::memcpy(&header, program_code.data(), sizeof(Tegra::Shader::Header));
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disable_flow_stack = false;
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ShaderCharacteristics shader_info{};
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bool can_proceed = ScanFlow(program_code, program_code.size(), main_offset, shader_info);
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if (can_proceed) {
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coverage_begin = shader_info.start;
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coverage_end = shader_info.end;
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if (shader_info.decompilable) {
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std::list<ShaderBlock>& blocks = shader_info.blocks;
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for (auto& block : blocks) {
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NodeBlock nodes;
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if (!block.ignore_branch) {
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nodes = DecodeRange(block.start, block.end);
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InsertControlFlow(nodes, block);
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} else {
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nodes = DecodeRange(block.start, block.end + 1);
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disable_flow_stack = true;
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auto insert_block = ([this](NodeBlock& nodes, u32 label) {
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if (label == exit_branch) {
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return;
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}
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basic_blocks.insert({label, nodes});
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});
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std::list<ShaderBlock>& blocks = shader_info.blocks;
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NodeBlock current_block;
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u32 current_label = exit_branch;
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for (auto& block : blocks) {
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if (shader_info.labels.count(block.start) != 0) {
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insert_block(current_block, current_label);
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current_block.clear();
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current_label = block.start;
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}
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if (!block.ignore_branch) {
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DecodeRangeInner(current_block, block.start, block.end);
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InsertControlFlow(current_block, block);
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} else {
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DecodeRangeInner(current_block, block.start, block.end + 1);
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}
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basic_blocks.insert({block.start, nodes});
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}
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insert_block(current_block, current_label);
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return;
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}
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LOG_WARNING(HW_GPU, "Flow Stack Removing Failed! Falling back to old method");
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// we can't decompile it, fallback to standard method
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for (const auto& block : shader_info.blocks) {
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basic_blocks.insert({block.start, DecodeRange(block.start, block.end + 1)});
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}
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return;
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}
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LOG_WARNING(HW_GPU, "Flow Analysis failed, falling back to brute force compiling");
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LOG_WARNING(HW_GPU, "Flow Analysis Failed! Falling back to brute force compiling");
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// Now we need to deal with an undecompilable shader. We need to brute force
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// a shader that captures every position.
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@ -78,12 +93,16 @@ void ShaderIR::Decode() {
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NodeBlock ShaderIR::DecodeRange(u32 begin, u32 end) {
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NodeBlock basic_block;
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for (u32 pc = begin; pc < (begin > end ? MAX_PROGRAM_LENGTH : end);) {
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pc = DecodeInstr(basic_block, pc);
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}
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DecodeRangeInner(basic_block, begin, end);
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return basic_block;
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}
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void ShaderIR::DecodeRangeInner(NodeBlock& bb, u32 begin, u32 end) {
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for (u32 pc = begin; pc < (begin > end ? MAX_PROGRAM_LENGTH : end);) {
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pc = DecodeInstr(bb, pc);
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}
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}
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void ShaderIR::InsertControlFlow(NodeBlock& bb, const ShaderBlock& block) {
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auto apply_conditions = ([&](const Condition& cond, Node n) -> Node {
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Node result = n;
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@ -98,9 +98,10 @@ u32 ShaderIR::DecodeOther(NodeBlock& bb, u32 pc) {
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} else {
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const u32 target = pc + 1;
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const Node op_a = GetConstBuffer(instr.cbuf36.index, instr.cbuf36.GetOffset());
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const Node convert = SignedOperation(OperationCode::IArithmeticShiftRight,
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true, PRECISE, op_a, Immediate(3));
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const Node operand = Operation(OperationCode::IAdd, PRECISE, convert, Immediate(target));
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const Node convert = SignedOperation(OperationCode::IArithmeticShiftRight, true,
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PRECISE, op_a, Immediate(3));
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const Node operand =
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Operation(OperationCode::IAdd, PRECISE, convert, Immediate(target));
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branch = Operation(OperationCode::BranchIndirect, convert);
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}
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@ -119,14 +120,14 @@ u32 ShaderIR::DecodeOther(NodeBlock& bb, u32 pc) {
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const Node index = GetRegister(instr.gpr8);
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const Node op_a =
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GetConstBufferIndirect(instr.cbuf36.index, instr.cbuf36.GetOffset() + 0, index);
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const Node convert = SignedOperation(OperationCode::IArithmeticShiftRight,
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true, PRECISE, op_a, Immediate(3));
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const Node convert = SignedOperation(OperationCode::IArithmeticShiftRight, true,
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PRECISE, op_a, Immediate(3));
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operand = Operation(OperationCode::IAdd, PRECISE, convert, Immediate(target));
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} else {
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const s32 target = pc + instr.brx.GetBranchExtend();
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const Node op_a = GetRegister(instr.gpr8);
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const Node convert = SignedOperation(OperationCode::IArithmeticShiftRight,
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true, PRECISE, op_a, Immediate(3));
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const Node convert = SignedOperation(OperationCode::IArithmeticShiftRight, true,
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PRECISE, op_a, Immediate(3));
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operand = Operation(OperationCode::IAdd, PRECISE, convert, Immediate(target));
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}
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const Node branch = Operation(OperationCode::BranchIndirect, operand);
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@ -143,6 +144,10 @@ u32 ShaderIR::DecodeOther(NodeBlock& bb, u32 pc) {
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UNIMPLEMENTED_IF_MSG(instr.bra.constant_buffer != 0,
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"Constant buffer flow is not supported");
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if (disable_flow_stack) {
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break;
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}
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// The SSY opcode tells the GPU where to re-converge divergent execution paths with SYNC.
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const u32 target = pc + instr.bra.GetBranchTarget();
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bb.push_back(
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@ -153,6 +158,10 @@ u32 ShaderIR::DecodeOther(NodeBlock& bb, u32 pc) {
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UNIMPLEMENTED_IF_MSG(instr.bra.constant_buffer != 0,
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"Constant buffer PBK is not supported");
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if (disable_flow_stack) {
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break;
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}
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// PBK pushes to a stack the address where BRK will jump to.
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const u32 target = pc + instr.bra.GetBranchTarget();
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bb.push_back(
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@ -164,6 +173,10 @@ u32 ShaderIR::DecodeOther(NodeBlock& bb, u32 pc) {
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UNIMPLEMENTED_IF_MSG(cc != Tegra::Shader::ConditionCode::T, "SYNC condition code used: {}",
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static_cast<u32>(cc));
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if (disable_flow_stack) {
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break;
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}
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// The SYNC opcode jumps to the address previously set by the SSY opcode
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bb.push_back(Operation(OperationCode::PopFlowStack, MetaStackClass::Ssy));
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break;
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@ -172,6 +185,9 @@ u32 ShaderIR::DecodeOther(NodeBlock& bb, u32 pc) {
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const Tegra::Shader::ConditionCode cc = instr.flow_condition_code;
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UNIMPLEMENTED_IF_MSG(cc != Tegra::Shader::ConditionCode::T, "BRK condition code used: {}",
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static_cast<u32>(cc));
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if (disable_flow_stack) {
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break;
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}
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// The BRK opcode jumps to the address previously set by the PBK opcode
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bb.push_back(Operation(OperationCode::PopFlowStack, MetaStackClass::Pbk));
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@ -148,12 +148,12 @@ enum class OperationCode {
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ImageStore, /// (MetaImage, float[N] coords) -> void
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Branch, /// (uint branch_target) -> void
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BranchIndirect,/// (uint branch_target) -> void
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PushFlowStack, /// (uint branch_target) -> void
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PopFlowStack, /// () -> void
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Exit, /// () -> void
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Discard, /// () -> void
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Branch, /// (uint branch_target) -> void
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BranchIndirect, /// (uint branch_target) -> void
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PushFlowStack, /// (uint branch_target) -> void
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PopFlowStack, /// () -> void
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Exit, /// () -> void
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Discard, /// () -> void
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EmitVertex, /// () -> void
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EndPrimitive, /// () -> void
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@ -123,10 +123,15 @@ public:
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return header;
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}
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bool IsFlowStackDisabled() const {
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return disable_flow_stack;
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}
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private:
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void Decode();
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NodeBlock DecodeRange(u32 begin, u32 end);
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void DecodeRangeInner(NodeBlock& bb, u32 begin, u32 end);
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void InsertControlFlow(NodeBlock& bb, const ShaderBlock& block);
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/**
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@ -320,6 +325,7 @@ private:
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const ProgramCode& program_code;
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const u32 main_offset;
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const std::size_t program_size;
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bool disable_flow_stack{};
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u32 coverage_begin{};
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u32 coverage_end{};
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