gl_renderer: Cache textures, framebuffers, and shaders based on CPU address.
This commit is contained in:
parent
16d65182f9
commit
d647d9550c
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@ -10,6 +10,7 @@
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#include "common/common_types.h"
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#include "common/swap.h"
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#include "core/hle/service/nvdrv/devices/nvdevice.h"
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#include "video_core/memory_manager.h"
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namespace Service::Nvidia::Devices {
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@ -251,8 +251,8 @@ std::string ReadCString(VAddr vaddr, std::size_t max_length) {
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return string;
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}
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void RasterizerMarkRegionCached(Tegra::GPUVAddr gpu_addr, u64 size, bool cached) {
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if (gpu_addr == 0) {
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void RasterizerMarkRegionCached(VAddr vaddr, u64 size, bool cached) {
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if (vaddr == 0) {
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return;
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}
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@ -261,19 +261,8 @@ void RasterizerMarkRegionCached(Tegra::GPUVAddr gpu_addr, u64 size, bool cached)
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// CPU pages, hence why we iterate on a CPU page basis (note: GPU page size is different). This
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// assumes the specified GPU address region is contiguous as well.
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u64 num_pages = ((gpu_addr + size - 1) >> PAGE_BITS) - (gpu_addr >> PAGE_BITS) + 1;
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for (unsigned i = 0; i < num_pages; ++i, gpu_addr += PAGE_SIZE) {
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boost::optional<VAddr> maybe_vaddr =
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Core::System::GetInstance().GPU().MemoryManager().GpuToCpuAddress(gpu_addr);
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// The GPU <-> CPU virtual memory mapping is not 1:1
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if (!maybe_vaddr) {
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LOG_ERROR(HW_Memory,
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"Trying to flush a cached region to an invalid physical address {:016X}",
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gpu_addr);
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continue;
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}
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VAddr vaddr = *maybe_vaddr;
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u64 num_pages = ((vaddr + size - 1) >> PAGE_BITS) - (vaddr >> PAGE_BITS) + 1;
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for (unsigned i = 0; i < num_pages; ++i, vaddr += PAGE_SIZE) {
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PageType& page_type = current_page_table->attributes[vaddr >> PAGE_BITS];
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if (cached) {
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@ -344,29 +333,19 @@ void RasterizerFlushVirtualRegion(VAddr start, u64 size, FlushMode mode) {
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const VAddr overlap_start = std::max(start, region_start);
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const VAddr overlap_end = std::min(end, region_end);
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const std::vector<Tegra::GPUVAddr> gpu_addresses =
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system_instance.GPU().MemoryManager().CpuToGpuAddress(overlap_start);
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if (gpu_addresses.empty()) {
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return;
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}
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const u64 overlap_size = overlap_end - overlap_start;
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for (const auto& gpu_address : gpu_addresses) {
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auto& rasterizer = system_instance.Renderer().Rasterizer();
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switch (mode) {
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case FlushMode::Flush:
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rasterizer.FlushRegion(gpu_address, overlap_size);
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break;
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case FlushMode::Invalidate:
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rasterizer.InvalidateRegion(gpu_address, overlap_size);
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break;
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case FlushMode::FlushAndInvalidate:
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rasterizer.FlushAndInvalidateRegion(gpu_address, overlap_size);
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break;
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}
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auto& rasterizer = system_instance.Renderer().Rasterizer();
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switch (mode) {
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case FlushMode::Flush:
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rasterizer.FlushRegion(overlap_start, overlap_size);
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break;
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case FlushMode::Invalidate:
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rasterizer.InvalidateRegion(overlap_start, overlap_size);
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break;
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case FlushMode::FlushAndInvalidate:
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rasterizer.FlushAndInvalidateRegion(overlap_start, overlap_size);
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break;
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}
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};
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@ -11,7 +11,6 @@
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#include <boost/icl/interval_map.hpp>
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#include "common/common_types.h"
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#include "core/memory_hook.h"
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#include "video_core/memory_manager.h"
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namespace Kernel {
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class Process;
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@ -179,7 +178,7 @@ enum class FlushMode {
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/**
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* Mark each page touching the region as cached.
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*/
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void RasterizerMarkRegionCached(Tegra::GPUVAddr gpu_addr, u64 size, bool cached);
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void RasterizerMarkRegionCached(VAddr vaddr, u64 size, bool cached);
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/**
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* Flushes and invalidates any externally cached rasterizer resources touching the given virtual
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@ -17,7 +17,7 @@ template <class T>
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class RasterizerCache : NonCopyable {
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public:
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/// Mark the specified region as being invalidated
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void InvalidateRegion(Tegra::GPUVAddr region_addr, size_t region_size) {
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void InvalidateRegion(VAddr region_addr, size_t region_size) {
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for (auto iter = cached_objects.cbegin(); iter != cached_objects.cend();) {
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const auto& object{iter->second};
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@ -33,7 +33,7 @@ public:
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protected:
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/// Tries to get an object from the cache with the specified address
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T TryGet(Tegra::GPUVAddr addr) const {
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T TryGet(VAddr addr) const {
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const auto& search{cached_objects.find(addr)};
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if (search != cached_objects.end()) {
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return search->second;
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@ -43,7 +43,7 @@ protected:
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}
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/// Gets a reference to the cache
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const std::unordered_map<Tegra::GPUVAddr, T>& GetCache() const {
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const std::unordered_map<VAddr, T>& GetCache() const {
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return cached_objects;
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}
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@ -74,5 +74,5 @@ protected:
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}
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private:
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std::unordered_map<Tegra::GPUVAddr, T> cached_objects;
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std::unordered_map<VAddr, T> cached_objects;
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};
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@ -27,14 +27,14 @@ public:
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virtual void FlushAll() = 0;
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/// Notify rasterizer that any caches of the specified region should be flushed to Switch memory
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virtual void FlushRegion(Tegra::GPUVAddr addr, u64 size) = 0;
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virtual void FlushRegion(VAddr addr, u64 size) = 0;
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/// Notify rasterizer that any caches of the specified region should be invalidated
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virtual void InvalidateRegion(Tegra::GPUVAddr addr, u64 size) = 0;
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virtual void InvalidateRegion(VAddr addr, u64 size) = 0;
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/// Notify rasterizer that any caches of the specified region should be flushed to Switch memory
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/// and invalidated
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virtual void FlushAndInvalidateRegion(Tegra::GPUVAddr addr, u64 size) = 0;
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virtual void FlushAndInvalidateRegion(VAddr addr, u64 size) = 0;
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/// Attempt to use a faster method to perform a display transfer with is_texture_copy = 0
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virtual bool AccelerateDisplayTransfer(const void* config) {
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@ -279,10 +279,9 @@ static constexpr auto RangeFromInterval(Map& map, const Interval& interval) {
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return boost::make_iterator_range(map.equal_range(interval));
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}
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void RasterizerOpenGL::UpdatePagesCachedCount(Tegra::GPUVAddr addr, u64 size, int delta) {
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const u64 page_start{addr >> Tegra::MemoryManager::PAGE_BITS};
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const u64 page_end{(addr + size + Tegra::MemoryManager::PAGE_SIZE - 1) >>
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Tegra::MemoryManager::PAGE_BITS};
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void RasterizerOpenGL::UpdatePagesCachedCount(VAddr addr, u64 size, int delta) {
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const u64 page_start{addr >> Memory::PAGE_BITS};
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const u64 page_end{(addr + size + Memory::PAGE_SIZE - 1) >> Memory::PAGE_BITS};
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// Interval maps will erase segments if count reaches 0, so if delta is negative we have to
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// subtract after iterating
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@ -294,10 +293,8 @@ void RasterizerOpenGL::UpdatePagesCachedCount(Tegra::GPUVAddr addr, u64 size, in
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const auto interval = pair.first & pages_interval;
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const int count = pair.second;
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const Tegra::GPUVAddr interval_start_addr = boost::icl::first(interval)
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<< Tegra::MemoryManager::PAGE_BITS;
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const Tegra::GPUVAddr interval_end_addr = boost::icl::last_next(interval)
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<< Tegra::MemoryManager::PAGE_BITS;
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const VAddr interval_start_addr = boost::icl::first(interval) << Memory::PAGE_BITS;
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const VAddr interval_end_addr = boost::icl::last_next(interval) << Memory::PAGE_BITS;
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const u64 interval_size = interval_end_addr - interval_start_addr;
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if (delta > 0 && count == delta)
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@ -578,17 +575,17 @@ void RasterizerOpenGL::FlushAll() {
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MICROPROFILE_SCOPE(OpenGL_CacheManagement);
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}
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void RasterizerOpenGL::FlushRegion(Tegra::GPUVAddr addr, u64 size) {
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void RasterizerOpenGL::FlushRegion(VAddr addr, u64 size) {
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MICROPROFILE_SCOPE(OpenGL_CacheManagement);
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}
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void RasterizerOpenGL::InvalidateRegion(Tegra::GPUVAddr addr, u64 size) {
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void RasterizerOpenGL::InvalidateRegion(VAddr addr, u64 size) {
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MICROPROFILE_SCOPE(OpenGL_CacheManagement);
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res_cache.InvalidateRegion(addr, size);
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shader_cache.InvalidateRegion(addr, size);
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}
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void RasterizerOpenGL::FlushAndInvalidateRegion(Tegra::GPUVAddr addr, u64 size) {
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void RasterizerOpenGL::FlushAndInvalidateRegion(VAddr addr, u64 size) {
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MICROPROFILE_SCOPE(OpenGL_CacheManagement);
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InvalidateRegion(addr, size);
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}
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@ -44,9 +44,9 @@ public:
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void Clear() override;
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void NotifyMaxwellRegisterChanged(u32 method) override;
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void FlushAll() override;
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void FlushRegion(Tegra::GPUVAddr addr, u64 size) override;
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void InvalidateRegion(Tegra::GPUVAddr addr, u64 size) override;
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void FlushAndInvalidateRegion(Tegra::GPUVAddr addr, u64 size) override;
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void FlushRegion(VAddr addr, u64 size) override;
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void InvalidateRegion(VAddr addr, u64 size) override;
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void FlushAndInvalidateRegion(VAddr addr, u64 size) override;
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bool AccelerateDisplayTransfer(const void* config) override;
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bool AccelerateTextureCopy(const void* config) override;
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bool AccelerateFill(const void* config) override;
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@ -33,11 +33,16 @@ struct FormatTuple {
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bool compressed;
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};
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static VAddr TryGetCpuAddr(Tegra::GPUVAddr gpu_addr) {
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auto& gpu{Core::System::GetInstance().GPU()};
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const auto cpu_addr{gpu.MemoryManager().GpuToCpuAddress(gpu_addr)};
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return cpu_addr ? *cpu_addr : 0;
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}
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/*static*/ SurfaceParams SurfaceParams::CreateForTexture(
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const Tegra::Texture::FullTextureInfo& config) {
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SurfaceParams params{};
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params.addr = config.tic.Address();
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params.addr = TryGetCpuAddr(config.tic.Address());
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params.is_tiled = config.tic.IsTiled();
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params.block_height = params.is_tiled ? config.tic.BlockHeight() : 0,
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params.pixel_format =
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/*static*/ SurfaceParams SurfaceParams::CreateForFramebuffer(
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const Tegra::Engines::Maxwell3D::Regs::RenderTargetConfig& config) {
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SurfaceParams params{};
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params.addr = config.Address();
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params.addr = TryGetCpuAddr(config.Address());
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params.is_tiled = true;
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params.block_height = Tegra::Texture::TICEntry::DefaultBlockHeight;
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params.pixel_format = PixelFormatFromRenderTargetFormat(config.format);
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/*static*/ SurfaceParams SurfaceParams::CreateForDepthBuffer(u32 zeta_width, u32 zeta_height,
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Tegra::GPUVAddr zeta_address,
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Tegra::DepthFormat format) {
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SurfaceParams params{};
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params.addr = zeta_address;
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params.addr = TryGetCpuAddr(zeta_address);
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params.is_tiled = true;
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params.block_height = Tegra::Texture::TICEntry::DefaultBlockHeight;
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params.pixel_format = PixelFormatFromDepthFormat(format);
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return format;
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}
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VAddr SurfaceParams::GetCpuAddr() const {
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auto& gpu = Core::System::GetInstance().GPU();
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return *gpu.MemoryManager().GpuToCpuAddress(addr);
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}
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static bool IsPixelFormatASTC(PixelFormat format) {
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switch (format) {
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case PixelFormat::ASTC_2D_4X4:
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@ -222,33 +220,28 @@ static bool IsFormatBCn(PixelFormat format) {
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}
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template <bool morton_to_gl, PixelFormat format>
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void MortonCopy(u32 stride, u32 block_height, u32 height, std::vector<u8>& gl_buffer,
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Tegra::GPUVAddr addr) {
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void MortonCopy(u32 stride, u32 block_height, u32 height, std::vector<u8>& gl_buffer, VAddr addr) {
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constexpr u32 bytes_per_pixel = SurfaceParams::GetFormatBpp(format) / CHAR_BIT;
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constexpr u32 gl_bytes_per_pixel = CachedSurface::GetGLBytesPerPixel(format);
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auto& gpu = Core::System::GetInstance().GPU();
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if (morton_to_gl) {
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// With the BCn formats (DXT and DXN), each 4x4 tile is swizzled instead of just individual
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// pixel values.
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const u32 tile_size{IsFormatBCn(format) ? 4U : 1U};
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const std::vector<u8> data =
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Tegra::Texture::UnswizzleTexture(*gpu.MemoryManager().GpuToCpuAddress(addr), tile_size,
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bytes_per_pixel, stride, height, block_height);
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const std::vector<u8> data = Tegra::Texture::UnswizzleTexture(
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addr, tile_size, bytes_per_pixel, stride, height, block_height);
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const size_t size_to_copy{std::min(gl_buffer.size(), data.size())};
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gl_buffer.assign(data.begin(), data.begin() + size_to_copy);
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} else {
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// TODO(bunnei): Assumes the default rendering GOB size of 16 (128 lines). We should
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// check the configuration for this and perform more generic un/swizzle
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LOG_WARNING(Render_OpenGL, "need to use correct swizzle/GOB parameters!");
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VideoCore::MortonCopyPixels128(
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stride, height, bytes_per_pixel, gl_bytes_per_pixel,
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Memory::GetPointer(*gpu.MemoryManager().GpuToCpuAddress(addr)), gl_buffer.data(),
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morton_to_gl);
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VideoCore::MortonCopyPixels128(stride, height, bytes_per_pixel, gl_bytes_per_pixel,
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Memory::GetPointer(addr), gl_buffer.data(), morton_to_gl);
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}
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}
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static constexpr std::array<void (*)(u32, u32, u32, std::vector<u8>&, Tegra::GPUVAddr),
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static constexpr std::array<void (*)(u32, u32, u32, std::vector<u8>&, VAddr),
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SurfaceParams::MaxPixelFormat>
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morton_to_gl_fns = {
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// clang-format off
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// clang-format on
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};
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static constexpr std::array<void (*)(u32, u32, u32, std::vector<u8>&, Tegra::GPUVAddr),
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static constexpr std::array<void (*)(u32, u32, u32, std::vector<u8>&, VAddr),
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SurfaceParams::MaxPixelFormat>
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gl_to_morton_fns = {
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// clang-format off
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@ -542,7 +535,7 @@ MICROPROFILE_DEFINE(OpenGL_SurfaceLoad, "OpenGL", "Surface Load", MP_RGB(128, 64
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void CachedSurface::LoadGLBuffer() {
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ASSERT(params.type != SurfaceType::Fill);
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const u8* const texture_src_data = Memory::GetPointer(params.GetCpuAddr());
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const u8* const texture_src_data = Memory::GetPointer(params.addr);
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ASSERT(texture_src_data);
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@ -567,7 +560,7 @@ void CachedSurface::LoadGLBuffer() {
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MICROPROFILE_DEFINE(OpenGL_SurfaceFlush, "OpenGL", "Surface Flush", MP_RGB(128, 192, 64));
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void CachedSurface::FlushGLBuffer() {
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u8* const dst_buffer = Memory::GetPointer(params.GetCpuAddr());
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u8* const dst_buffer = Memory::GetPointer(params.addr);
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ASSERT(dst_buffer);
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ASSERT(gl_buffer.size() ==
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@ -764,11 +757,6 @@ Surface RasterizerCacheOpenGL::GetSurface(const SurfaceParams& params, bool pres
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return {};
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}
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auto& gpu = Core::System::GetInstance().GPU();
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// Don't try to create any entries in the cache if the address of the texture is invalid.
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if (gpu.MemoryManager().GpuToCpuAddress(params.addr) == boost::none)
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return {};
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// Look up surface in the cache based on address
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Surface surface{TryGet(params.addr)};
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if (surface) {
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@ -858,10 +846,8 @@ Surface RasterizerCacheOpenGL::RecreateSurface(const Surface& surface,
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"reinterpretation but the texture is tiled.");
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}
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size_t remaining_size = new_params.SizeInBytes() - params.SizeInBytes();
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auto address = Core::System::GetInstance().GPU().MemoryManager().GpuToCpuAddress(
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new_params.addr + params.SizeInBytes());
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std::vector<u8> data(remaining_size);
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Memory::ReadBlock(*address, data.data(), data.size());
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Memory::ReadBlock(new_params.addr + params.SizeInBytes(), data.data(), data.size());
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glBufferSubData(GL_PIXEL_PACK_BUFFER, params.SizeInBytes(), remaining_size, data.data());
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}
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@ -888,30 +874,8 @@ Surface RasterizerCacheOpenGL::RecreateSurface(const Surface& surface,
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return new_surface;
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}
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Surface RasterizerCacheOpenGL::TryFindFramebufferSurface(VAddr cpu_addr) const {
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// Tries to find the GPU address of a framebuffer based on the CPU address. This is because
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// final output framebuffers are specified by CPU address, but internally our GPU cache uses
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// GPU addresses. We iterate through all cached framebuffers, and compare their starting CPU
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// address to the one provided. This is obviously not great, and won't work if the
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// framebuffer overlaps surfaces.
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std::vector<Surface> surfaces;
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for (const auto& surface : GetCache()) {
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const auto& params = surface.second->GetSurfaceParams();
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const VAddr surface_cpu_addr = params.GetCpuAddr();
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if (cpu_addr >= surface_cpu_addr && cpu_addr < (surface_cpu_addr + params.size_in_bytes)) {
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ASSERT_MSG(cpu_addr == surface_cpu_addr, "overlapping surfaces are unsupported");
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surfaces.push_back(surface.second);
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}
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}
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if (surfaces.empty()) {
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return {};
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}
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ASSERT_MSG(surfaces.size() == 1, ">1 surface is unsupported");
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return surfaces[0];
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Surface RasterizerCacheOpenGL::TryFindFramebufferSurface(VAddr addr) const {
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return TryGet(addr);
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}
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void RasterizerCacheOpenGL::ReserveSurface(const Surface& surface) {
|
||||
|
|
|
@ -638,9 +638,6 @@ struct SurfaceParams {
|
|||
GetFormatBpp(pixel_format) / CHAR_BIT;
|
||||
}
|
||||
|
||||
/// Returns the CPU virtual address for this surface
|
||||
VAddr GetCpuAddr() const;
|
||||
|
||||
/// Creates SurfaceParams from a texture configuration
|
||||
static SurfaceParams CreateForTexture(const Tegra::Texture::FullTextureInfo& config);
|
||||
|
||||
|
@ -671,7 +668,7 @@ struct SurfaceParams {
|
|||
std::tie(other.pixel_format, other.type, other.cache_width, other.cache_height);
|
||||
}
|
||||
|
||||
Tegra::GPUVAddr addr;
|
||||
VAddr addr;
|
||||
bool is_tiled;
|
||||
u32 block_height;
|
||||
PixelFormat pixel_format;
|
||||
|
@ -712,7 +709,7 @@ class CachedSurface final {
|
|||
public:
|
||||
CachedSurface(const SurfaceParams& params);
|
||||
|
||||
Tegra::GPUVAddr GetAddr() const {
|
||||
VAddr GetAddr() const {
|
||||
return params.addr;
|
||||
}
|
||||
|
||||
|
@ -763,8 +760,8 @@ public:
|
|||
/// Flushes the surface to Switch memory
|
||||
void FlushSurface(const Surface& surface);
|
||||
|
||||
/// Tries to find a framebuffer GPU address based on the provided CPU address
|
||||
Surface TryFindFramebufferSurface(VAddr cpu_addr) const;
|
||||
/// Tries to find a framebuffer using on the provided CPU address
|
||||
Surface TryFindFramebufferSurface(VAddr addr) const;
|
||||
|
||||
private:
|
||||
void LoadSurface(const Surface& surface);
|
||||
|
|
|
@ -12,21 +12,17 @@
|
|||
namespace OpenGL {
|
||||
|
||||
/// Gets the address for the specified shader stage program
|
||||
static Tegra::GPUVAddr GetShaderAddress(Maxwell::ShaderProgram program) {
|
||||
static VAddr GetShaderAddress(Maxwell::ShaderProgram program) {
|
||||
auto& gpu = Core::System::GetInstance().GPU().Maxwell3D();
|
||||
auto& shader_config = gpu.regs.shader_config[static_cast<size_t>(program)];
|
||||
|
||||
return gpu.regs.code_address.CodeAddress() + shader_config.offset;
|
||||
return *gpu.memory_manager.GpuToCpuAddress(gpu.regs.code_address.CodeAddress() +
|
||||
shader_config.offset);
|
||||
}
|
||||
|
||||
/// Gets the shader program code from memory for the specified address
|
||||
static GLShader::ProgramCode GetShaderCode(Tegra::GPUVAddr addr) {
|
||||
auto& gpu = Core::System::GetInstance().GPU().Maxwell3D();
|
||||
|
||||
static GLShader::ProgramCode GetShaderCode(VAddr addr) {
|
||||
GLShader::ProgramCode program_code(GLShader::MAX_PROGRAM_CODE_LENGTH);
|
||||
const boost::optional<VAddr> cpu_address{gpu.memory_manager.GpuToCpuAddress(addr)};
|
||||
Memory::ReadBlock(*cpu_address, program_code.data(), program_code.size() * sizeof(u64));
|
||||
|
||||
Memory::ReadBlock(addr, program_code.data(), program_code.size() * sizeof(u64));
|
||||
return program_code;
|
||||
}
|
||||
|
||||
|
@ -55,7 +51,7 @@ static void SetShaderUniformBlockBindings(GLuint shader) {
|
|||
sizeof(GLShader::MaxwellUniformData));
|
||||
}
|
||||
|
||||
CachedShader::CachedShader(Tegra::GPUVAddr addr, Maxwell::ShaderProgram program_type)
|
||||
CachedShader::CachedShader(VAddr addr, Maxwell::ShaderProgram program_type)
|
||||
: addr{addr}, program_type{program_type}, setup{GetShaderCode(addr)} {
|
||||
|
||||
GLShader::ProgramResult program_result;
|
||||
|
@ -113,7 +109,7 @@ GLint CachedShader::GetUniformLocation(const std::string& name) {
|
|||
}
|
||||
|
||||
Shader ShaderCacheOpenGL::GetStageProgram(Maxwell::ShaderProgram program) {
|
||||
const Tegra::GPUVAddr program_addr{GetShaderAddress(program)};
|
||||
const VAddr program_addr{GetShaderAddress(program)};
|
||||
|
||||
// Look up shader in the cache based on address
|
||||
Shader shader{TryGet(program_addr)};
|
||||
|
|
|
@ -8,7 +8,6 @@
|
|||
#include <unordered_map>
|
||||
|
||||
#include "common/common_types.h"
|
||||
#include "video_core/memory_manager.h"
|
||||
#include "video_core/rasterizer_cache.h"
|
||||
#include "video_core/renderer_opengl/gl_resource_manager.h"
|
||||
#include "video_core/renderer_opengl/gl_shader_gen.h"
|
||||
|
@ -21,10 +20,10 @@ using Maxwell = Tegra::Engines::Maxwell3D::Regs;
|
|||
|
||||
class CachedShader final {
|
||||
public:
|
||||
CachedShader(Tegra::GPUVAddr addr, Maxwell::ShaderProgram program_type);
|
||||
CachedShader(VAddr addr, Maxwell::ShaderProgram program_type);
|
||||
|
||||
/// Gets the address of the shader in guest memory, required for cache management
|
||||
Tegra::GPUVAddr GetAddr() const {
|
||||
VAddr GetAddr() const {
|
||||
return addr;
|
||||
}
|
||||
|
||||
|
@ -50,7 +49,7 @@ public:
|
|||
GLint GetUniformLocation(const std::string& name);
|
||||
|
||||
private:
|
||||
Tegra::GPUVAddr addr;
|
||||
VAddr addr;
|
||||
Maxwell::ShaderProgram program_type;
|
||||
GLShader::ShaderSetup setup;
|
||||
GLShader::ShaderEntries entries;
|
||||
|
|
Reference in New Issue