shader_ir: Remove composite primitives and use temporals instead
This commit is contained in:
ReinUsesLisp
parent
bb12f99b20
commit
d911740e5d
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@ -2,6 +2,7 @@
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <array>
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#include <string>
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#include <string_view>
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#include <variant>
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@ -770,49 +771,6 @@ private:
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return {};
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}
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std::string AssignComposite(Operation operation) {
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const auto& meta = std::get<MetaComponents>(operation.GetMeta());
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const std::string composite = code.GenerateTemporal();
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code.AddLine("vec4 " + composite + " = " + Visit(operation[0]) + ';');
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constexpr u32 composite_size = 4;
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for (u32 i = 0; i < composite_size; ++i) {
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const auto gpr = std::get<GprNode>(*operation[i + 1]).GetIndex();
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if (gpr == Register::ZeroIndex) {
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continue;
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}
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code.AddLine(GetRegister(gpr) + " = " + composite +
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GetSwizzle(meta.GetSourceComponent(i)) + ';');
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}
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return {};
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}
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std::string AssignCompositeHalf(Operation operation) {
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const auto& meta = std::get<MetaComponents>(operation.GetMeta());
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const std::string composite = code.GenerateTemporal();
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code.AddLine("vec4 " + composite + " = " + Visit(operation[0]) + ';');
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const auto ReadComponent = [&](u32 component) {
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if (component < meta.count) {
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return composite + '[' + std::to_string(meta.GetSourceComponent(component)) + ']';
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}
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return std::string("0");
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};
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const auto dst1 = std::get<GprNode>(*operation[1]).GetIndex();
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const std::string src1 = "vec2(" + ReadComponent(0) + ", " + ReadComponent(1) + ')';
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code.AddLine(GetRegister(dst1) + " = utof(packHalf2x16(" + src1 + "))");
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if (meta.count > 2) {
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const auto dst2 = std::get<GprNode>(*operation[2]).GetIndex();
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const std::string src2 = "vec2(" + ReadComponent(2) + ", " + ReadComponent(3) + ')';
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code.AddLine(GetRegister(dst2) + " = utof(packHalf2x16(" + src2 + "));");
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}
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return {};
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}
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std::string Composite(Operation operation) {
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std::string value = "vec4(";
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for (std::size_t i = 0; i < 4; ++i) {
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@ -1018,6 +976,10 @@ private:
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Visit(operation[1]) + ")[1]))";
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}
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std::string HPack2(Operation operation) {
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return "utof(packHalf2x16(vec2(" + Visit(operation[0]) + ", " + Visit(operation[1]) + ")))";
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}
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template <Type type>
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std::string LogicalLessThan(Operation operation) {
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return GenerateBinaryInfix(operation, "<", Type::Bool, type, type);
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@ -1137,30 +1099,35 @@ private:
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}
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std::string F4Texture(Operation operation) {
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const auto meta = std::get<MetaTexture>(operation.GetMeta());
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std::string expr = GenerateTexture(operation, "texture");
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if (std::get<MetaTexture>(operation.GetMeta()).sampler.IsShadow()) {
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if (meta.sampler.IsShadow()) {
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expr = "vec4(" + expr + ')';
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}
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return expr;
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return expr + GetSwizzle(meta.element);
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}
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std::string F4TextureLod(Operation operation) {
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const auto meta = std::get<MetaTexture>(operation.GetMeta());
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std::string expr = GenerateTexture(operation, "textureLod");
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if (std::get<MetaTexture>(operation.GetMeta()).sampler.IsShadow()) {
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if (meta.sampler.IsShadow()) {
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expr = "vec4(" + expr + ')';
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}
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return expr;
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return expr + GetSwizzle(meta.element);
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}
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std::string F4TextureGather(Operation operation) {
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const bool is_shadow = std::get<MetaTexture>(operation.GetMeta()).sampler.IsShadow();
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if (is_shadow) {
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return GenerateTexture(operation, "textureGather",
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const auto meta = std::get<MetaTexture>(operation.GetMeta());
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std::string expr;
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if (meta.sampler.IsShadow()) {
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expr = GenerateTexture(operation, "textureGather",
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[](std::string ref_z) { return ref_z; });
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} else {
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return GenerateTexture(operation, "textureGather",
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expr = GenerateTexture(operation, "textureGather",
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[](std::string comp) { return "ftoi(" + comp + ')'; });
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}
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return expr + GetSwizzle(meta.element);
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}
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std::string F4TextureQueryDimensions(Operation operation) {
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@ -1168,20 +1135,26 @@ private:
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const std::string sampler = GetSampler(meta.sampler);
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const std::string lod = VisitOperand(operation, 0, Type::Int);
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const std::string sizes = code.GenerateTemporal();
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code.AddLine("ivec2 " + sizes + " = textureSize(" + sampler + ", " + lod + ");");
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const std::string mip_level = "textureQueryLevels(" + sampler + ')';
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return "itof(ivec4(" + sizes + ", 0, " + mip_level + "))";
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switch (meta.element) {
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case 0:
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case 1:
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return "textureSize(" + sampler + ", " + lod + ')' + GetSwizzle(meta.element);
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case 2:
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return "0";
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case 3:
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return "textureQueryLevels(" + sampler + ')';
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}
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UNREACHABLE();
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return "0";
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}
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std::string F4TextureQueryLod(Operation operation) {
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const std::string tmp = code.GenerateTemporal();
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code.AddLine("vec2 " + tmp + " = " + GenerateTexture(operation, "textureQueryLod") +
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" * vec2(256);");
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return "vec4(itof(int(" + tmp + ".y)), utof(uint(" + tmp + ".x)), 0, 0)";
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const auto& meta = std::get<MetaTexture>(operation.GetMeta());
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if (meta.element < 2) {
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return "itof(int((" + GenerateTexture(operation, "textureQueryLod") + " * vec2(256))" +
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GetSwizzle(meta.element) + "))";
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}
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return "0";
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}
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std::string F4TexelFetch(Operation operation) {
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@ -1206,7 +1179,7 @@ private:
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}
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}
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expr += ')';
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return expr;
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return expr + GetSwizzle(meta.element);
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}
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std::string Branch(Operation operation) {
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@ -1328,10 +1301,7 @@ private:
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static constexpr OperationDecompilersArray operation_decompilers = {
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&GLSLDecompiler::Assign,
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&GLSLDecompiler::AssignComposite,
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&GLSLDecompiler::AssignCompositeHalf,
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&GLSLDecompiler::Composite,
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&GLSLDecompiler::Select,
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&GLSLDecompiler::Add<Type::Float>,
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@ -1403,6 +1373,7 @@ private:
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&GLSLDecompiler::HMergeF32,
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&GLSLDecompiler::HMergeH0,
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&GLSLDecompiler::HMergeH1,
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&GLSLDecompiler::HPack2,
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&GLSLDecompiler::LogicalAssign,
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&GLSLDecompiler::LogicalAnd,
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@ -90,15 +90,10 @@ u32 ShaderIR::DecodeMemory(BasicBlock& bb, u32 pc) {
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const Node op_b =
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GetConstBufferIndirect(instr.cbuf36.index, instr.cbuf36.offset + 4, index);
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const Node composite =
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Operation(OperationCode::Composite, op_a, op_b, GetRegister(Register::ZeroIndex),
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GetRegister(Register::ZeroIndex));
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MetaComponents meta{{0, 1, 2, 3}};
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bb.push_back(Operation(OperationCode::AssignComposite, meta, composite,
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GetRegister(instr.gpr0), GetRegister(instr.gpr0.Value() + 1),
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GetRegister(Register::ZeroIndex),
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GetRegister(Register::ZeroIndex)));
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SetTemporal(bb, 0, op_a);
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SetTemporal(bb, 1, op_b);
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SetRegister(bb, instr.gpr0, GetTemporal(0));
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SetRegister(bb, instr.gpr0.Value() + 1, GetTemporal(1));
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break;
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}
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default:
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@ -172,10 +167,6 @@ u32 ShaderIR::DecodeMemory(BasicBlock& bb, u32 pc) {
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break;
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}
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case OpCode::Id::TEX: {
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Tegra::Shader::TextureType texture_type{instr.tex.texture_type};
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const bool is_array = instr.tex.array != 0;
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const bool depth_compare = instr.tex.UsesMiscMode(TextureMiscMode::DC);
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const auto process_mode = instr.tex.GetTextureProcessMode();
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UNIMPLEMENTED_IF_MSG(instr.tex.UsesMiscMode(TextureMiscMode::AOFFI),
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"AOFFI is not implemented");
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@ -183,27 +174,12 @@ u32 ShaderIR::DecodeMemory(BasicBlock& bb, u32 pc) {
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LOG_WARNING(HW_GPU, "TEX.NODEP implementation is incomplete");
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}
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const Node texture = GetTexCode(instr, texture_type, process_mode, depth_compare, is_array);
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MetaComponents meta;
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std::array<Node, 4> dest;
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std::size_t dest_elem = 0;
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for (std::size_t elem = 0; elem < 4; ++elem) {
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if (!instr.tex.IsComponentEnabled(elem)) {
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// Skip disabled components
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continue;
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}
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meta.components_map[dest_elem] = static_cast<u32>(elem);
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dest[dest_elem] = GetRegister(instr.gpr0.Value() + dest_elem);
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++dest_elem;
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}
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std::generate(dest.begin() + dest_elem, dest.end(),
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[&]() { return GetRegister(Register::ZeroIndex); });
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bb.push_back(Operation(OperationCode::AssignComposite, std::move(meta), texture, dest[0],
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dest[1], dest[2], dest[3]));
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const TextureType texture_type{instr.tex.texture_type};
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const bool is_array = instr.tex.array != 0;
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const bool depth_compare = instr.tex.UsesMiscMode(TextureMiscMode::DC);
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const auto process_mode = instr.tex.GetTextureProcessMode();
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WriteTexInstructionFloat(
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bb, instr, GetTexCode(instr, texture_type, process_mode, depth_compare, is_array));
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break;
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}
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case OpCode::Id::TEXS: {
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@ -216,13 +192,13 @@ u32 ShaderIR::DecodeMemory(BasicBlock& bb, u32 pc) {
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LOG_WARNING(HW_GPU, "TEXS.NODEP implementation is incomplete");
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}
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const Node texture =
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const Node4 components =
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GetTexsCode(instr, texture_type, process_mode, depth_compare, is_array);
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if (instr.texs.fp32_flag) {
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WriteTexsInstructionFloat(bb, instr, texture);
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WriteTexsInstructionFloat(bb, instr, components);
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} else {
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WriteTexsInstructionHalfFloat(bb, instr, texture);
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WriteTexsInstructionHalfFloat(bb, instr, components);
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}
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break;
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}
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@ -242,27 +218,8 @@ u32 ShaderIR::DecodeMemory(BasicBlock& bb, u32 pc) {
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const auto texture_type = instr.tld4.texture_type.Value();
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const bool depth_compare = instr.tld4.UsesMiscMode(TextureMiscMode::DC);
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const bool is_array = instr.tld4.array != 0;
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const Node texture = GetTld4Code(instr, texture_type, depth_compare, is_array);
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MetaComponents meta_components;
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std::array<Node, 4> dest;
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std::size_t dest_elem = 0;
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for (std::size_t elem = 0; elem < 4; ++elem) {
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if (!instr.tex.IsComponentEnabled(elem)) {
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// Skip disabled components
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continue;
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}
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meta_components.components_map[dest_elem] = static_cast<u32>(elem);
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dest[dest_elem] = GetRegister(instr.gpr0.Value() + dest_elem);
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++dest_elem;
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}
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std::generate(dest.begin() + dest_elem, dest.end(),
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[&]() { return GetRegister(Register::ZeroIndex); });
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bb.push_back(Operation(OperationCode::AssignComposite, std::move(meta_components), texture,
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dest[0], dest[1], dest[2], dest[3]));
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WriteTexInstructionFloat(bb, instr,
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GetTld4Code(instr, texture_type, depth_compare, is_array));
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break;
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}
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case OpCode::Id::TLD4S: {
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@ -277,28 +234,34 @@ u32 ShaderIR::DecodeMemory(BasicBlock& bb, u32 pc) {
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const Node op_a = GetRegister(instr.gpr8);
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const Node op_b = GetRegister(instr.gpr20);
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std::vector<Node> params;
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std::vector<Node> coords;
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// TODO(Subv): Figure out how the sampler type is encoded in the TLD4S instruction.
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if (depth_compare) {
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// Note: TLD4S coordinate encoding works just like TEXS's
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const Node op_y = GetRegister(instr.gpr8.Value() + 1);
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params.push_back(op_a);
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params.push_back(op_y);
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params.push_back(op_b);
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coords.push_back(op_a);
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coords.push_back(op_y);
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coords.push_back(op_b);
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} else {
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params.push_back(op_a);
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params.push_back(op_b);
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coords.push_back(op_a);
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coords.push_back(op_b);
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}
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const auto num_coords = static_cast<u32>(params.size());
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params.push_back(Immediate(static_cast<u32>(instr.tld4s.component)));
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const auto num_coords = static_cast<u32>(coords.size());
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coords.push_back(Immediate(static_cast<u32>(instr.tld4s.component)));
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const auto& sampler =
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GetSampler(instr.sampler, TextureType::Texture2D, false, depth_compare);
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MetaTexture meta{sampler, num_coords};
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WriteTexsInstructionFloat(
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bb, instr, Operation(OperationCode::F4TextureGather, meta, std::move(params)));
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Node4 values;
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for (u32 element = 0; element < values.size(); ++element) {
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auto params = coords;
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MetaTexture meta{sampler, element, num_coords};
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values[element] =
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Operation(OperationCode::F4TextureGather, std::move(meta), std::move(params));
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}
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WriteTexsInstructionFloat(bb, instr, values);
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break;
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}
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case OpCode::Id::TXQ: {
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@ -314,18 +277,15 @@ u32 ShaderIR::DecodeMemory(BasicBlock& bb, u32 pc) {
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switch (instr.txq.query_type) {
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case Tegra::Shader::TextureQueryType::Dimension: {
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MetaTexture meta_texture{sampler};
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const MetaComponents meta_components{{0, 1, 2, 3}};
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const Node texture = Operation(OperationCode::F4TextureQueryDimensions, meta_texture,
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GetRegister(instr.gpr8));
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std::array<Node, 4> dest;
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for (std::size_t i = 0; i < dest.size(); ++i) {
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dest[i] = GetRegister(instr.gpr0.Value() + i);
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for (u32 element = 0; element < 4; ++element) {
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MetaTexture meta{sampler, element};
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const Node value = Operation(OperationCode::F4TextureQueryDimensions,
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std::move(meta), GetRegister(instr.gpr8));
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SetTemporal(bb, element, value);
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}
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for (u32 i = 0; i < 4; ++i) {
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SetRegister(bb, instr.gpr0.Value() + i, GetTemporal(i));
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}
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bb.push_back(Operation(OperationCode::AssignComposite, meta_components, texture,
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dest[0], dest[1], dest[2], dest[3]));
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break;
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}
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default:
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@ -366,14 +326,17 @@ u32 ShaderIR::DecodeMemory(BasicBlock& bb, u32 pc) {
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texture_type = TextureType::Texture2D;
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}
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MetaTexture meta_texture{sampler, static_cast<u32>(coords.size())};
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const Node texture =
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Operation(OperationCode::F4TextureQueryLod, meta_texture, std::move(coords));
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for (u32 element = 0; element < 2; ++element) {
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auto params = coords;
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MetaTexture meta_texture{sampler, element, static_cast<u32>(coords.size())};
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const Node value =
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Operation(OperationCode::F4TextureQueryLod, meta_texture, std::move(params));
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SetTemporal(bb, element, value);
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}
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for (u32 element = 0; element < 2; ++element) {
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SetRegister(bb, instr.gpr0.Value() + element, GetTemporal(element));
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}
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const MetaComponents meta_composite{{0, 1, 2, 3}};
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bb.push_back(Operation(OperationCode::AssignComposite, meta_composite, texture,
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GetRegister(instr.gpr0), GetRegister(instr.gpr0.Value() + 1),
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GetRegister(Register::ZeroIndex), GetRegister(Register::ZeroIndex)));
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break;
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}
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case OpCode::Id::TLDS: {
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@ -388,8 +351,7 @@ u32 ShaderIR::DecodeMemory(BasicBlock& bb, u32 pc) {
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LOG_WARNING(HW_GPU, "TMML.NODEP implementation is incomplete");
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}
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const Node texture = GetTldsCode(instr, texture_type, is_array);
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WriteTexsInstructionFloat(bb, instr, texture);
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WriteTexsInstructionFloat(bb, instr, GetTldsCode(instr, texture_type, is_array));
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break;
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}
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default:
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@ -419,54 +381,77 @@ const Sampler& ShaderIR::GetSampler(const Tegra::Shader::Sampler& sampler, Textu
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return *used_samplers.emplace(entry).first;
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}
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void ShaderIR::WriteTexsInstructionFloat(BasicBlock& bb, Instruction instr, Node texture) {
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void ShaderIR::WriteTexInstructionFloat(BasicBlock& bb, Instruction instr,
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const Node4& components) {
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u32 dest_elem = 0;
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for (u32 elem = 0; elem < 4; ++elem) {
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if (!instr.tex.IsComponentEnabled(elem)) {
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// Skip disabled components
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continue;
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}
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SetTemporal(bb, dest_elem++, components[elem]);
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}
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// After writing values in temporals, move them to the real registers
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for (u32 i = 0; i < dest_elem; ++i) {
|
||||
SetRegister(bb, instr.gpr0.Value() + i, GetTemporal(i));
|
||||
}
|
||||
}
|
||||
|
||||
void ShaderIR::WriteTexsInstructionFloat(BasicBlock& bb, Instruction instr,
|
||||
const Node4& components) {
|
||||
// TEXS has two destination registers and a swizzle. The first two elements in the swizzle
|
||||
// go into gpr0+0 and gpr0+1, and the rest goes into gpr28+0 and gpr28+1
|
||||
|
||||
MetaComponents meta;
|
||||
std::array<Node, 4> dest;
|
||||
for (u32 component = 0; component < 4; ++component) {
|
||||
if (!instr.texs.IsComponentEnabled(component)) {
|
||||
continue;
|
||||
}
|
||||
meta.components_map[meta.count] = component;
|
||||
|
||||
if (meta.count < 2) {
|
||||
// Write the first two swizzle components to gpr0 and gpr0+1
|
||||
dest[meta.count] = GetRegister(instr.gpr0.Value() + meta.count % 2);
|
||||
} else {
|
||||
ASSERT(instr.texs.HasTwoDestinations());
|
||||
// Write the rest of the swizzle components to gpr28 and gpr28+1
|
||||
dest[meta.count] = GetRegister(instr.gpr28.Value() + meta.count % 2);
|
||||
}
|
||||
++meta.count;
|
||||
}
|
||||
|
||||
std::generate(dest.begin() + meta.count, dest.end(),
|
||||
[&]() { return GetRegister(Register::ZeroIndex); });
|
||||
|
||||
bb.push_back(Operation(OperationCode::AssignComposite, meta, texture, dest[0], dest[1], dest[2],
|
||||
dest[3]));
|
||||
}
|
||||
|
||||
void ShaderIR::WriteTexsInstructionHalfFloat(BasicBlock& bb, Instruction instr, Node texture) {
|
||||
// TEXS.F16 destionation registers are packed in two registers in pairs (just like any half
|
||||
// float instruction).
|
||||
|
||||
MetaComponents meta;
|
||||
u32 dest_elem = 0;
|
||||
for (u32 component = 0; component < 4; ++component) {
|
||||
if (!instr.texs.IsComponentEnabled(component))
|
||||
continue;
|
||||
meta.components_map[meta.count++] = component;
|
||||
SetTemporal(bb, dest_elem++, components[component]);
|
||||
}
|
||||
if (meta.count == 0)
|
||||
|
||||
for (u32 i = 0; i < dest_elem; ++i) {
|
||||
if (i < 2) {
|
||||
// Write the first two swizzle components to gpr0 and gpr0+1
|
||||
SetRegister(bb, instr.gpr0.Value() + i % 2, GetTemporal(i));
|
||||
} else {
|
||||
ASSERT(instr.texs.HasTwoDestinations());
|
||||
// Write the rest of the swizzle components to gpr28 and gpr28+1
|
||||
SetRegister(bb, instr.gpr28.Value() + i % 2, GetTemporal(i));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void ShaderIR::WriteTexsInstructionHalfFloat(BasicBlock& bb, Instruction instr,
|
||||
const Node4& components) {
|
||||
// TEXS.F16 destionation registers are packed in two registers in pairs (just like any half
|
||||
// float instruction).
|
||||
|
||||
Node4 values;
|
||||
u32 dest_elem = 0;
|
||||
for (u32 component = 0; component < 4; ++component) {
|
||||
if (!instr.texs.IsComponentEnabled(component))
|
||||
continue;
|
||||
values[dest_elem++] = components[component];
|
||||
}
|
||||
if (dest_elem == 0)
|
||||
return;
|
||||
|
||||
bb.push_back(Operation(OperationCode::AssignCompositeHalf, meta, texture,
|
||||
GetRegister(instr.gpr0), GetRegister(instr.gpr28)));
|
||||
std::generate(values.begin() + dest_elem, values.end(), [&]() { return Immediate(0); });
|
||||
|
||||
const Node first_value = Operation(OperationCode::HPack2, values[0], values[1]);
|
||||
if (dest_elem <= 2) {
|
||||
SetRegister(bb, instr.gpr0, first_value);
|
||||
return;
|
||||
}
|
||||
|
||||
Node ShaderIR::GetTextureCode(Instruction instr, TextureType texture_type,
|
||||
SetTemporal(bb, 0, first_value);
|
||||
SetTemporal(bb, 1, Operation(OperationCode::HPack2, values[2], values[3]));
|
||||
|
||||
SetRegister(bb, instr.gpr0, GetTemporal(0));
|
||||
SetRegister(bb, instr.gpr28, GetTemporal(1));
|
||||
}
|
||||
|
||||
Node4 ShaderIR::GetTextureCode(Instruction instr, TextureType texture_type,
|
||||
TextureProcessMode process_mode, bool depth_compare, bool is_array,
|
||||
std::size_t array_offset, std::size_t bias_offset,
|
||||
std::vector<Node>&& coords) {
|
||||
|
|
@ -495,23 +480,30 @@ Node ShaderIR::GetTextureCode(Instruction instr, TextureType texture_type,
|
|||
std::optional<u32> array_offset_value;
|
||||
if (is_array)
|
||||
array_offset_value = static_cast<u32>(array_offset);
|
||||
MetaTexture meta{sampler, static_cast<u32>(coords.size()), array_offset_value};
|
||||
std::vector<Node> params = std::move(coords);
|
||||
|
||||
const auto coords_count = static_cast<u32>(coords.size());
|
||||
|
||||
if (process_mode != TextureProcessMode::None && gl_lod_supported) {
|
||||
if (process_mode == TextureProcessMode::LZ) {
|
||||
params.push_back(Immediate(0.0f));
|
||||
coords.push_back(Immediate(0.0f));
|
||||
} else {
|
||||
// If present, lod or bias are always stored in the register indexed by the gpr20 field
|
||||
// with an offset depending on the usage of the other registers
|
||||
params.push_back(GetRegister(instr.gpr20.Value() + bias_offset));
|
||||
// If present, lod or bias are always stored in the register indexed by the gpr20
|
||||
// field with an offset depending on the usage of the other registers
|
||||
coords.push_back(GetRegister(instr.gpr20.Value() + bias_offset));
|
||||
}
|
||||
}
|
||||
|
||||
return Operation(read_method, meta, std::move(params));
|
||||
Node4 values;
|
||||
for (u32 element = 0; element < values.size(); ++element) {
|
||||
auto params = coords;
|
||||
MetaTexture meta{sampler, element, coords_count, array_offset_value};
|
||||
values[element] = Operation(read_method, std::move(meta), std::move(params));
|
||||
}
|
||||
|
||||
Node ShaderIR::GetTexCode(Instruction instr, TextureType texture_type,
|
||||
return values;
|
||||
}
|
||||
|
||||
Node4 ShaderIR::GetTexCode(Instruction instr, TextureType texture_type,
|
||||
TextureProcessMode process_mode, bool depth_compare, bool is_array) {
|
||||
const bool lod_bias_enabled =
|
||||
(process_mode != TextureProcessMode::None && process_mode != TextureProcessMode::LZ);
|
||||
|
|
@ -551,7 +543,7 @@ Node ShaderIR::GetTexCode(Instruction instr, TextureType texture_type,
|
|||
0, std::move(coords));
|
||||
}
|
||||
|
||||
Node ShaderIR::GetTexsCode(Instruction instr, TextureType texture_type,
|
||||
Node4 ShaderIR::GetTexsCode(Instruction instr, TextureType texture_type,
|
||||
TextureProcessMode process_mode, bool depth_compare, bool is_array) {
|
||||
const bool lod_bias_enabled =
|
||||
(process_mode != TextureProcessMode::None && process_mode != TextureProcessMode::LZ);
|
||||
|
|
@ -593,7 +585,7 @@ Node ShaderIR::GetTexsCode(Instruction instr, TextureType texture_type,
|
|||
(coord_count > 2 ? 1 : 0), std::move(coords));
|
||||
}
|
||||
|
||||
Node ShaderIR::GetTld4Code(Instruction instr, TextureType texture_type, bool depth_compare,
|
||||
Node4 ShaderIR::GetTld4Code(Instruction instr, TextureType texture_type, bool depth_compare,
|
||||
bool is_array) {
|
||||
const std::size_t coord_count = GetCoordCount(texture_type);
|
||||
const std::size_t total_coord_count = coord_count + (is_array ? 1 : 0);
|
||||
|
|
@ -604,24 +596,31 @@ Node ShaderIR::GetTld4Code(Instruction instr, TextureType texture_type, bool dep
|
|||
// First coordinate index is the gpr8 or gpr8 + 1 when arrays are used
|
||||
const u64 coord_register = array_register + (is_array ? 1 : 0);
|
||||
|
||||
std::vector<Node> params;
|
||||
std::vector<Node> coords;
|
||||
|
||||
for (size_t i = 0; i < coord_count; ++i) {
|
||||
params.push_back(GetRegister(coord_register + i));
|
||||
coords.push_back(GetRegister(coord_register + i));
|
||||
}
|
||||
std::optional<u32> array_offset;
|
||||
if (is_array) {
|
||||
array_offset = static_cast<u32>(params.size());
|
||||
params.push_back(GetRegister(array_register));
|
||||
array_offset = static_cast<u32>(coords.size());
|
||||
coords.push_back(GetRegister(array_register));
|
||||
}
|
||||
|
||||
const auto& sampler = GetSampler(instr.sampler, texture_type, is_array, depth_compare);
|
||||
MetaTexture meta{sampler, static_cast<u32>(params.size()), array_offset};
|
||||
|
||||
return Operation(OperationCode::F4TextureGather, std::move(meta), std::move(params));
|
||||
Node4 values;
|
||||
for (u32 element = 0; element < values.size(); ++element) {
|
||||
auto params = coords;
|
||||
MetaTexture meta{sampler, element, static_cast<u32>(coords.size()), array_offset};
|
||||
values[element] =
|
||||
Operation(OperationCode::F4TextureGather, std::move(meta), std::move(params));
|
||||
}
|
||||
|
||||
Node ShaderIR::GetTldsCode(Instruction instr, TextureType texture_type, bool is_array) {
|
||||
return values;
|
||||
}
|
||||
|
||||
Node4 ShaderIR::GetTldsCode(Instruction instr, TextureType texture_type, bool is_array) {
|
||||
const std::size_t type_coord_count = GetCoordCount(texture_type);
|
||||
const std::size_t total_coord_count = type_coord_count + (is_array ? 1 : 0);
|
||||
const bool lod_enabled = instr.tlds.GetTextureProcessMode() == TextureProcessMode::LL;
|
||||
|
|
@ -636,36 +635,41 @@ Node ShaderIR::GetTldsCode(Instruction instr, TextureType texture_type, bool is_
|
|||
? static_cast<u64>(instr.gpr20.Value())
|
||||
: coord_register + 1;
|
||||
|
||||
std::vector<Node> params;
|
||||
std::vector<Node> coords;
|
||||
|
||||
for (std::size_t i = 0; i < type_coord_count; ++i) {
|
||||
const bool last = (i == (type_coord_count - 1)) && (type_coord_count > 1);
|
||||
params.push_back(GetRegister(last ? last_coord_register : coord_register + i));
|
||||
coords.push_back(GetRegister(last ? last_coord_register : coord_register + i));
|
||||
}
|
||||
std::optional<u32> array_offset;
|
||||
if (is_array) {
|
||||
array_offset = static_cast<u32>(params.size());
|
||||
params.push_back(GetRegister(array_register));
|
||||
array_offset = static_cast<u32>(coords.size());
|
||||
coords.push_back(GetRegister(array_register));
|
||||
}
|
||||
const auto coords_count = static_cast<u32>(params.size());
|
||||
const auto coords_count = static_cast<u32>(coords.size());
|
||||
|
||||
if (lod_enabled) {
|
||||
// When lod is used always is in grp20
|
||||
params.push_back(GetRegister(instr.gpr20));
|
||||
coords.push_back(GetRegister(instr.gpr20));
|
||||
} else {
|
||||
params.push_back(Immediate(0));
|
||||
coords.push_back(Immediate(0));
|
||||
}
|
||||
|
||||
const auto& sampler = GetSampler(instr.sampler, texture_type, is_array, false);
|
||||
MetaTexture meta{sampler, coords_count, array_offset};
|
||||
|
||||
return Operation(OperationCode::F4TexelFetch, std::move(meta), std::move(params));
|
||||
Node4 values;
|
||||
for (u32 element = 0; element < values.size(); ++element) {
|
||||
auto params = coords;
|
||||
MetaTexture meta{sampler, element, coords_count, array_offset};
|
||||
values[element] =
|
||||
Operation(OperationCode::F4TexelFetch, std::move(meta), std::move(params));
|
||||
}
|
||||
return values;
|
||||
}
|
||||
|
||||
std::tuple<std::size_t, std::size_t> ShaderIR::ValidateAndGetCoordinateElement(
|
||||
TextureType texture_type, bool depth_compare, bool is_array, bool lod_bias_enabled,
|
||||
std::size_t max_coords, std::size_t max_inputs) {
|
||||
|
||||
const std::size_t coord_count = GetCoordCount(texture_type);
|
||||
|
||||
std::size_t total_coord_count = coord_count + (is_array ? 1 : 0) + (depth_compare ? 1 : 0);
|
||||
|
|
|
|||
|
|
@ -121,6 +121,10 @@ Node ShaderIR::GetLocalMemory(Node address) {
|
|||
return StoreNode(LmemNode(address));
|
||||
}
|
||||
|
||||
Node ShaderIR::GetTemporal(u32 id) {
|
||||
return GetRegister(Register::ZeroIndex + 1 + id);
|
||||
}
|
||||
|
||||
Node ShaderIR::GetOperandAbsNegFloat(Node value, bool absolute, bool negate) {
|
||||
if (absolute) {
|
||||
value = Operation(OperationCode::FAbsolute, NO_PRECISE, value);
|
||||
|
|
@ -348,6 +352,10 @@ void ShaderIR::SetLocalMemory(BasicBlock& bb, Node address, Node value) {
|
|||
bb.push_back(Operation(OperationCode::Assign, GetLocalMemory(address), value));
|
||||
}
|
||||
|
||||
void ShaderIR::SetTemporal(BasicBlock& bb, u32 id, Node value) {
|
||||
SetRegister(bb, Register::ZeroIndex + 1 + id, value);
|
||||
}
|
||||
|
||||
Node ShaderIR::BitfieldExtract(Node value, u32 offset, u32 bits) {
|
||||
return Operation(OperationCode::UBitfieldExtract, NO_PRECISE, value, Immediate(offset),
|
||||
Immediate(bits));
|
||||
|
|
|
|||
|
|
@ -4,6 +4,7 @@
|
|||
|
||||
#pragma once
|
||||
|
||||
#include <array>
|
||||
#include <cstring>
|
||||
#include <map>
|
||||
#include <set>
|
||||
|
|
@ -37,16 +38,14 @@ using NodeData =
|
|||
std::variant<OperationNode, ConditionalNode, GprNode, ImmediateNode, InternalFlagNode,
|
||||
PredicateNode, AbufNode, CbufNode, LmemNode, GmemNode, CommentNode>;
|
||||
using Node = const NodeData*;
|
||||
using Node4 = std::array<Node, 4>;
|
||||
using BasicBlock = std::vector<Node>;
|
||||
|
||||
constexpr u32 MAX_PROGRAM_LENGTH = 0x1000;
|
||||
|
||||
enum class OperationCode {
|
||||
Assign, /// (float& dest, float src) -> void
|
||||
AssignComposite, /// (MetaComponents, float4 src, float&[4] dst) -> void
|
||||
AssignCompositeHalf, /// (MetaComponents, float4 src, float&[2] dst) -> void
|
||||
|
||||
Composite, /// (float[4] values) -> float4
|
||||
Select, /// (MetaArithmetic, bool pred, float a, float b) -> float
|
||||
|
||||
FAdd, /// (MetaArithmetic, float a, float b) -> float
|
||||
|
|
@ -117,6 +116,7 @@ enum class OperationCode {
|
|||
HMergeF32, /// (f16vec2 src) -> float
|
||||
HMergeH0, /// (f16vec2 dest, f16vec2 src) -> f16vec2
|
||||
HMergeH1, /// (f16vec2 dest, f16vec2 src) -> f16vec2
|
||||
HPack2, /// (float a, float b) -> f16vec2
|
||||
|
||||
LogicalAssign, /// (bool& dst, bool src) -> void
|
||||
LogicalAnd, /// (bool a, bool b) -> bool
|
||||
|
|
@ -270,24 +270,16 @@ struct MetaHalfArithmetic {
|
|||
|
||||
struct MetaTexture {
|
||||
const Sampler& sampler;
|
||||
u32 element{};
|
||||
u32 coords_count{};
|
||||
std::optional<u32> array_index;
|
||||
};
|
||||
|
||||
struct MetaComponents {
|
||||
std::array<u32, 4> components_map{};
|
||||
u32 count{};
|
||||
|
||||
u32 GetSourceComponent(u32 dest_index) const {
|
||||
return components_map[dest_index];
|
||||
}
|
||||
};
|
||||
|
||||
constexpr MetaArithmetic PRECISE = {true};
|
||||
constexpr MetaArithmetic NO_PRECISE = {false};
|
||||
constexpr MetaHalfArithmetic HALF_NO_PRECISE = {false};
|
||||
|
||||
using Meta = std::variant<MetaArithmetic, MetaHalfArithmetic, MetaTexture, MetaComponents>;
|
||||
using Meta = std::variant<MetaArithmetic, MetaHalfArithmetic, MetaTexture>;
|
||||
|
||||
/// Holds any kind of operation that can be done in the IR
|
||||
class OperationNode final {
|
||||
|
|
@ -643,6 +635,8 @@ private:
|
|||
Node GetInternalFlag(InternalFlag flag, bool negated = false);
|
||||
/// Generates a node representing a local memory address
|
||||
Node GetLocalMemory(Node address);
|
||||
/// Generates a temporal, internally it uses a post-RZ register
|
||||
Node GetTemporal(u32 id);
|
||||
|
||||
/// Sets a register. src value must be a number-evaluated node.
|
||||
void SetRegister(BasicBlock& bb, Tegra::Shader::Register dest, Node src);
|
||||
|
|
@ -652,6 +646,8 @@ private:
|
|||
void SetInternalFlag(BasicBlock& bb, InternalFlag flag, Node value);
|
||||
/// Sets a local memory address. address and value must be a number-evaluated node
|
||||
void SetLocalMemory(BasicBlock& bb, Node address, Node value);
|
||||
/// Sets a temporal. Internally it uses a post-RZ register
|
||||
void SetTemporal(BasicBlock& bb, u32 id, Node value);
|
||||
|
||||
/// Conditionally absolute/negated float. Absolute is applied first
|
||||
Node GetOperandAbsNegFloat(Node value, bool absolute, bool negate);
|
||||
|
|
@ -692,29 +688,33 @@ private:
|
|||
/// Extracts a sequence of bits from a node
|
||||
Node BitfieldExtract(Node value, u32 offset, u32 bits);
|
||||
|
||||
void WriteTexsInstructionFloat(BasicBlock& bb, Tegra::Shader::Instruction instr, Node texture);
|
||||
void WriteTexInstructionFloat(BasicBlock& bb, Tegra::Shader::Instruction instr,
|
||||
const Node4& components);
|
||||
|
||||
void WriteTexsInstructionFloat(BasicBlock& bb, Tegra::Shader::Instruction instr,
|
||||
const Node4& components);
|
||||
void WriteTexsInstructionHalfFloat(BasicBlock& bb, Tegra::Shader::Instruction instr,
|
||||
Node texture);
|
||||
const Node4& components);
|
||||
|
||||
Node GetTexCode(Tegra::Shader::Instruction instr, Tegra::Shader::TextureType texture_type,
|
||||
Node4 GetTexCode(Tegra::Shader::Instruction instr, Tegra::Shader::TextureType texture_type,
|
||||
Tegra::Shader::TextureProcessMode process_mode, bool depth_compare,
|
||||
bool is_array);
|
||||
|
||||
Node GetTexsCode(Tegra::Shader::Instruction instr, Tegra::Shader::TextureType texture_type,
|
||||
Node4 GetTexsCode(Tegra::Shader::Instruction instr, Tegra::Shader::TextureType texture_type,
|
||||
Tegra::Shader::TextureProcessMode process_mode, bool depth_compare,
|
||||
bool is_array);
|
||||
|
||||
Node GetTld4Code(Tegra::Shader::Instruction instr, Tegra::Shader::TextureType texture_type,
|
||||
Node4 GetTld4Code(Tegra::Shader::Instruction instr, Tegra::Shader::TextureType texture_type,
|
||||
bool depth_compare, bool is_array);
|
||||
|
||||
Node GetTldsCode(Tegra::Shader::Instruction instr, Tegra::Shader::TextureType texture_type,
|
||||
Node4 GetTldsCode(Tegra::Shader::Instruction instr, Tegra::Shader::TextureType texture_type,
|
||||
bool is_array);
|
||||
|
||||
std::tuple<std::size_t, std::size_t> ValidateAndGetCoordinateElement(
|
||||
Tegra::Shader::TextureType texture_type, bool depth_compare, bool is_array,
|
||||
bool lod_bias_enabled, std::size_t max_coords, std::size_t max_inputs);
|
||||
|
||||
Node GetTextureCode(Tegra::Shader::Instruction instr, Tegra::Shader::TextureType texture_type,
|
||||
Node4 GetTextureCode(Tegra::Shader::Instruction instr, Tegra::Shader::TextureType texture_type,
|
||||
Tegra::Shader::TextureProcessMode process_mode, bool depth_compare,
|
||||
bool is_array, std::size_t array_offset, std::size_t bias_offset,
|
||||
std::vector<Node>&& coords);
|
||||
|
|
|
|||
Reference in New Issue