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Merge pull request #9406 from vonchenplus/topology

video_core: Adjust topology update logic and Adjust Clear Manage
This commit is contained in:
bunnei 2022-12-12 14:37:06 -08:00 committed by GitHub
commit da58eb6208
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4 changed files with 36 additions and 32 deletions

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@ -46,21 +46,26 @@ void DrawManager::ProcessMethodCall(u32 method, u32 argument) {
SetInlineIndexBuffer(regs.inline_index_4x8.index2); SetInlineIndexBuffer(regs.inline_index_4x8.index2);
SetInlineIndexBuffer(regs.inline_index_4x8.index3); SetInlineIndexBuffer(regs.inline_index_4x8.index3);
break; break;
case MAXWELL3D_REG_INDEX(topology_override): case MAXWELL3D_REG_INDEX(vertex_array_instance_first):
use_topology_override = true; case MAXWELL3D_REG_INDEX(vertex_array_instance_subsequent): {
LOG_WARNING(HW_GPU, "(STUBBED) called");
break; break;
}
default: default:
break; break;
} }
} }
void DrawManager::Clear(u32 layer_count) { void DrawManager::Clear(u32 layer_count) {
if (maxwell3d->ShouldExecute()) {
maxwell3d->rasterizer->Clear(layer_count); maxwell3d->rasterizer->Clear(layer_count);
} }
}
void DrawManager::DrawDeferred() { void DrawManager::DrawDeferred() {
if (draw_state.draw_mode != DrawMode::Instance || draw_state.instance_count == 0) if (draw_state.draw_mode != DrawMode::Instance || draw_state.instance_count == 0) {
return; return;
}
DrawEnd(draw_state.instance_count + 1, true); DrawEnd(draw_state.instance_count + 1, true);
draw_state.instance_count = 0; draw_state.instance_count = 0;
} }
@ -115,8 +120,9 @@ void DrawManager::DrawEnd(u32 instance_count, bool force_draw) {
const auto& regs{maxwell3d->regs}; const auto& regs{maxwell3d->regs};
switch (draw_state.draw_mode) { switch (draw_state.draw_mode) {
case DrawMode::Instance: case DrawMode::Instance:
if (!force_draw) if (!force_draw) {
break; break;
}
[[fallthrough]]; [[fallthrough]];
case DrawMode::General: case DrawMode::General:
draw_state.base_instance = regs.global_base_instance_index; draw_state.base_instance = regs.global_base_instance_index;
@ -156,11 +162,12 @@ void DrawManager::DrawIndexSmall(u32 argument) {
ProcessDraw(true, 1); ProcessDraw(true, 1);
} }
void DrawManager::ProcessTopologyOverride() { void DrawManager::UpdateTopology() {
if (!use_topology_override)
return;
const auto& regs{maxwell3d->regs}; const auto& regs{maxwell3d->regs};
switch (regs.primitive_topology_control) {
case PrimitiveTopologyControl::UseInBeginMethods:
break;
case PrimitiveTopologyControl::UseSeparateState:
switch (regs.topology_override) { switch (regs.topology_override) {
case PrimitiveTopologyOverride::None: case PrimitiveTopologyOverride::None:
break; break;
@ -177,15 +184,18 @@ void DrawManager::ProcessTopologyOverride() {
draw_state.topology = static_cast<PrimitiveTopology>(regs.topology_override); draw_state.topology = static_cast<PrimitiveTopology>(regs.topology_override);
break; break;
} }
break;
}
} }
void DrawManager::ProcessDraw(bool draw_indexed, u32 instance_count) { void DrawManager::ProcessDraw(bool draw_indexed, u32 instance_count) {
LOG_TRACE(HW_GPU, "called, topology={}, count={}", draw_state.topology, LOG_TRACE(HW_GPU, "called, topology={}, count={}", draw_state.topology,
draw_indexed ? draw_state.index_buffer.count : draw_state.vertex_buffer.count); draw_indexed ? draw_state.index_buffer.count : draw_state.vertex_buffer.count);
ProcessTopologyOverride(); UpdateTopology();
if (maxwell3d->ShouldExecute()) if (maxwell3d->ShouldExecute()) {
maxwell3d->rasterizer->Draw(draw_indexed, instance_count); maxwell3d->rasterizer->Draw(draw_indexed, instance_count);
} }
}
} // namespace Tegra::Engines } // namespace Tegra::Engines

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@ -10,6 +10,7 @@ class RasterizerInterface;
} }
namespace Tegra::Engines { namespace Tegra::Engines {
using PrimitiveTopologyControl = Maxwell3D::Regs::PrimitiveTopologyControl;
using PrimitiveTopology = Maxwell3D::Regs::PrimitiveTopology; using PrimitiveTopology = Maxwell3D::Regs::PrimitiveTopology;
using PrimitiveTopologyOverride = Maxwell3D::Regs::PrimitiveTopologyOverride; using PrimitiveTopologyOverride = Maxwell3D::Regs::PrimitiveTopologyOverride;
using IndexBuffer = Maxwell3D::Regs::IndexBuffer; using IndexBuffer = Maxwell3D::Regs::IndexBuffer;
@ -58,12 +59,11 @@ private:
void DrawIndexSmall(u32 argument); void DrawIndexSmall(u32 argument);
void ProcessTopologyOverride(); void UpdateTopology();
void ProcessDraw(bool draw_indexed, u32 instance_count); void ProcessDraw(bool draw_indexed, u32 instance_count);
Maxwell3D* maxwell3d{}; Maxwell3D* maxwell3d{};
State draw_state{}; State draw_state{};
bool use_topology_override{};
}; };
} // namespace Tegra::Engines } // namespace Tegra::Engines

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@ -138,9 +138,6 @@ void RasterizerOpenGL::LoadDiskResources(u64 title_id, std::stop_token stop_load
void RasterizerOpenGL::Clear(u32 layer_count) { void RasterizerOpenGL::Clear(u32 layer_count) {
MICROPROFILE_SCOPE(OpenGL_Clears); MICROPROFILE_SCOPE(OpenGL_Clears);
if (!maxwell3d->ShouldExecute()) {
return;
}
const auto& regs = maxwell3d->regs; const auto& regs = maxwell3d->regs;
bool use_color{}; bool use_color{};

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@ -216,9 +216,6 @@ void RasterizerVulkan::Draw(bool is_indexed, u32 instance_count) {
void RasterizerVulkan::Clear(u32 layer_count) { void RasterizerVulkan::Clear(u32 layer_count) {
MICROPROFILE_SCOPE(Vulkan_Clearing); MICROPROFILE_SCOPE(Vulkan_Clearing);
if (!maxwell3d->ShouldExecute()) {
return;
}
FlushWork(); FlushWork();
query_cache.UpdateCounters(); query_cache.UpdateCounters();