Merge pull request #2446 from ReinUsesLisp/tid
shader: Implement S2R Tid{XYZ} and CtaId{XYZ}
This commit is contained in:
commit
e3608578e4
|
@ -31,6 +31,8 @@ using Tegra::Shader::IpaInterpMode;
|
|||
using Tegra::Shader::IpaMode;
|
||||
using Tegra::Shader::IpaSampleMode;
|
||||
using Tegra::Shader::Register;
|
||||
|
||||
using namespace std::string_literals;
|
||||
using namespace VideoCommon::Shader;
|
||||
|
||||
using Maxwell = Tegra::Engines::Maxwell3D::Regs;
|
||||
|
@ -93,11 +95,9 @@ private:
|
|||
};
|
||||
|
||||
/// Generates code to use for a swizzle operation.
|
||||
std::string GetSwizzle(u32 elem) {
|
||||
ASSERT(elem <= 3);
|
||||
std::string swizzle = ".";
|
||||
swizzle += "xyzw"[elem];
|
||||
return swizzle;
|
||||
constexpr const char* GetSwizzle(u32 element) {
|
||||
constexpr std::array<const char*, 4> swizzle = {".x", ".y", ".z", ".w"};
|
||||
return swizzle.at(element);
|
||||
}
|
||||
|
||||
/// Translate topology
|
||||
|
@ -636,7 +636,7 @@ private:
|
|||
if (stage != ShaderStage::Fragment) {
|
||||
return GeometryPass("position") + GetSwizzle(element);
|
||||
} else {
|
||||
return element == 3 ? "1.0f" : "gl_FragCoord" + GetSwizzle(element);
|
||||
return element == 3 ? "1.0f" : ("gl_FragCoord"s + GetSwizzle(element));
|
||||
}
|
||||
case Attribute::Index::PointCoord:
|
||||
switch (element) {
|
||||
|
@ -921,7 +921,7 @@ private:
|
|||
target = [&]() -> std::string {
|
||||
switch (const auto attribute = abuf->GetIndex(); abuf->GetIndex()) {
|
||||
case Attribute::Index::Position:
|
||||
return "position" + GetSwizzle(abuf->GetElement());
|
||||
return "position"s + GetSwizzle(abuf->GetElement());
|
||||
case Attribute::Index::PointSize:
|
||||
return "gl_PointSize";
|
||||
case Attribute::Index::ClipDistances0123:
|
||||
|
@ -1526,6 +1526,16 @@ private:
|
|||
return "uintBitsToFloat(config_pack[2])";
|
||||
}
|
||||
|
||||
template <u32 element>
|
||||
std::string LocalInvocationId(Operation) {
|
||||
return "utof(gl_LocalInvocationID"s + GetSwizzle(element) + ')';
|
||||
}
|
||||
|
||||
template <u32 element>
|
||||
std::string WorkGroupId(Operation) {
|
||||
return "utof(gl_WorkGroupID"s + GetSwizzle(element) + ')';
|
||||
}
|
||||
|
||||
static constexpr OperationDecompilersArray operation_decompilers = {
|
||||
&GLSLDecompiler::Assign,
|
||||
|
||||
|
@ -1665,6 +1675,12 @@ private:
|
|||
&GLSLDecompiler::EndPrimitive,
|
||||
|
||||
&GLSLDecompiler::YNegate,
|
||||
&GLSLDecompiler::LocalInvocationId<0>,
|
||||
&GLSLDecompiler::LocalInvocationId<1>,
|
||||
&GLSLDecompiler::LocalInvocationId<2>,
|
||||
&GLSLDecompiler::WorkGroupId<0>,
|
||||
&GLSLDecompiler::WorkGroupId<1>,
|
||||
&GLSLDecompiler::WorkGroupId<2>,
|
||||
};
|
||||
|
||||
std::string GetRegister(u32 index) const {
|
||||
|
|
|
@ -1035,6 +1035,18 @@ private:
|
|||
return {};
|
||||
}
|
||||
|
||||
template <u32 element>
|
||||
Id LocalInvocationId(Operation) {
|
||||
UNIMPLEMENTED();
|
||||
return {};
|
||||
}
|
||||
|
||||
template <u32 element>
|
||||
Id WorkGroupId(Operation) {
|
||||
UNIMPLEMENTED();
|
||||
return {};
|
||||
}
|
||||
|
||||
Id DeclareBuiltIn(spv::BuiltIn builtin, spv::StorageClass storage, Id type,
|
||||
const std::string& name) {
|
||||
const Id id = OpVariable(type, storage);
|
||||
|
@ -1291,6 +1303,12 @@ private:
|
|||
&SPIRVDecompiler::EndPrimitive,
|
||||
|
||||
&SPIRVDecompiler::YNegate,
|
||||
&SPIRVDecompiler::LocalInvocationId<0>,
|
||||
&SPIRVDecompiler::LocalInvocationId<1>,
|
||||
&SPIRVDecompiler::LocalInvocationId<2>,
|
||||
&SPIRVDecompiler::WorkGroupId<0>,
|
||||
&SPIRVDecompiler::WorkGroupId<1>,
|
||||
&SPIRVDecompiler::WorkGroupId<2>,
|
||||
};
|
||||
|
||||
const ShaderIR& ir;
|
||||
|
|
|
@ -14,6 +14,7 @@ using Tegra::Shader::ConditionCode;
|
|||
using Tegra::Shader::Instruction;
|
||||
using Tegra::Shader::OpCode;
|
||||
using Tegra::Shader::Register;
|
||||
using Tegra::Shader::SystemVariable;
|
||||
|
||||
u32 ShaderIR::DecodeOther(NodeBlock& bb, u32 pc) {
|
||||
const Instruction instr = {program_code[pc]};
|
||||
|
@ -59,20 +60,33 @@ u32 ShaderIR::DecodeOther(NodeBlock& bb, u32 pc) {
|
|||
break;
|
||||
}
|
||||
case OpCode::Id::MOV_SYS: {
|
||||
const Node value = [&]() {
|
||||
switch (instr.sys20) {
|
||||
case Tegra::Shader::SystemVariable::InvocationInfo: {
|
||||
case SystemVariable::Ydirection:
|
||||
return Operation(OperationCode::YNegate);
|
||||
case SystemVariable::InvocationInfo:
|
||||
LOG_WARNING(HW_GPU, "MOV_SYS instruction with InvocationInfo is incomplete");
|
||||
SetRegister(bb, instr.gpr0, Immediate(0u));
|
||||
break;
|
||||
}
|
||||
case Tegra::Shader::SystemVariable::Ydirection: {
|
||||
// Config pack's third value is Y_NEGATE's state.
|
||||
SetRegister(bb, instr.gpr0, Operation(OperationCode::YNegate));
|
||||
break;
|
||||
}
|
||||
return Immediate(0u);
|
||||
case SystemVariable::TidX:
|
||||
return Operation(OperationCode::LocalInvocationIdX);
|
||||
case SystemVariable::TidY:
|
||||
return Operation(OperationCode::LocalInvocationIdY);
|
||||
case SystemVariable::TidZ:
|
||||
return Operation(OperationCode::LocalInvocationIdZ);
|
||||
case SystemVariable::CtaIdX:
|
||||
return Operation(OperationCode::WorkGroupIdX);
|
||||
case SystemVariable::CtaIdY:
|
||||
return Operation(OperationCode::WorkGroupIdY);
|
||||
case SystemVariable::CtaIdZ:
|
||||
return Operation(OperationCode::WorkGroupIdZ);
|
||||
default:
|
||||
UNIMPLEMENTED_MSG("Unhandled system move: {}", static_cast<u32>(instr.sys20.Value()));
|
||||
UNIMPLEMENTED_MSG("Unhandled system move: {}",
|
||||
static_cast<u32>(instr.sys20.Value()));
|
||||
return Immediate(0u);
|
||||
}
|
||||
}();
|
||||
SetRegister(bb, instr.gpr0, value);
|
||||
|
||||
break;
|
||||
}
|
||||
case OpCode::Id::BRA: {
|
||||
|
|
|
@ -182,6 +182,12 @@ enum class OperationCode {
|
|||
EndPrimitive, /// () -> void
|
||||
|
||||
YNegate, /// () -> float
|
||||
LocalInvocationIdX, /// () -> uint
|
||||
LocalInvocationIdY, /// () -> uint
|
||||
LocalInvocationIdZ, /// () -> uint
|
||||
WorkGroupIdX, /// () -> uint
|
||||
WorkGroupIdY, /// () -> uint
|
||||
WorkGroupIdZ, /// () -> uint
|
||||
|
||||
Amount,
|
||||
};
|
||||
|
|
Reference in New Issue