Refactors and name corrections.
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b3118ee316
commit
e64c41efe8
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@ -9,7 +9,7 @@
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namespace Tegra::Engines::Upload {
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namespace Tegra::Engines::Upload {
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State::State(MemoryManager& memory_manager, Data& regs)
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State::State(MemoryManager& memory_manager, Registers& regs)
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: memory_manager(memory_manager), regs(regs) {}
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: memory_manager(memory_manager), regs(regs) {}
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void State::ProcessExec(const bool is_linear) {
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void State::ProcessExec(const bool is_linear) {
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@ -23,24 +23,25 @@ void State::ProcessData(const u32 data, const bool is_last_call) {
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const u32 sub_copy_size = std::min(4U, copy_size - write_offset);
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const u32 sub_copy_size = std::min(4U, copy_size - write_offset);
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std::memcpy(&inner_buffer[write_offset], &data, sub_copy_size);
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std::memcpy(&inner_buffer[write_offset], &data, sub_copy_size);
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write_offset += sub_copy_size;
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write_offset += sub_copy_size;
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if (is_last_call) {
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if (!is_last_call) {
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const GPUVAddr address{regs.dest.Address()};
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return;
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if (is_linear) {
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}
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memory_manager.WriteBlock(address, inner_buffer.data(), copy_size);
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const GPUVAddr address{regs.dest.Address()};
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} else {
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if (is_linear) {
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UNIMPLEMENTED_IF(regs.dest.z != 0);
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memory_manager.WriteBlock(address, inner_buffer.data(), copy_size);
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UNIMPLEMENTED_IF(regs.dest.depth != 1);
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} else {
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UNIMPLEMENTED_IF(regs.dest.BlockWidth() != 1);
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UNIMPLEMENTED_IF(regs.dest.z != 0);
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UNIMPLEMENTED_IF(regs.dest.BlockDepth() != 1);
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UNIMPLEMENTED_IF(regs.dest.depth != 1);
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const std::size_t dst_size = Tegra::Texture::CalculateSize(
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UNIMPLEMENTED_IF(regs.dest.BlockWidth() != 1);
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true, 1, regs.dest.width, regs.dest.height, 1, regs.dest.BlockHeight(), 1);
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UNIMPLEMENTED_IF(regs.dest.BlockDepth() != 1);
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std::vector<u8> tmp_buffer(dst_size);
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const std::size_t dst_size = Tegra::Texture::CalculateSize(
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memory_manager.ReadBlock(address, tmp_buffer.data(), dst_size);
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true, 1, regs.dest.width, regs.dest.height, 1, regs.dest.BlockHeight(), 1);
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Tegra::Texture::SwizzleKepler(regs.dest.width, regs.dest.height, regs.dest.x,
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tmp_buffer.resize(dst_size);
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regs.dest.y, regs.dest.BlockHeight(), copy_size,
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memory_manager.ReadBlock(address, tmp_buffer.data(), dst_size);
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inner_buffer.data(), tmp_buffer.data());
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Tegra::Texture::SwizzleKepler(regs.dest.width, regs.dest.height, regs.dest.x, regs.dest.y,
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memory_manager.WriteBlock(address, tmp_buffer.data(), dst_size);
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regs.dest.BlockHeight(), copy_size, inner_buffer.data(),
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}
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tmp_buffer.data());
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memory_manager.WriteBlock(address, tmp_buffer.data(), dst_size);
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}
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}
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}
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}
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@ -16,7 +16,7 @@ class MemoryManager;
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namespace Tegra::Engines::Upload {
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namespace Tegra::Engines::Upload {
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struct Data {
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struct Registers {
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u32 line_length_in;
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u32 line_length_in;
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u32 line_count;
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u32 line_count;
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@ -56,7 +56,7 @@ struct Data {
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class State {
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class State {
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public:
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public:
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State(MemoryManager& memory_manager, Data& regs);
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State(MemoryManager& memory_manager, Registers& regs);
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~State() = default;
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~State() = default;
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void ProcessExec(const bool is_linear);
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void ProcessExec(const bool is_linear);
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@ -66,8 +66,9 @@ private:
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u32 write_offset = 0;
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u32 write_offset = 0;
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u32 copy_size = 0;
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u32 copy_size = 0;
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std::vector<u8> inner_buffer;
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std::vector<u8> inner_buffer;
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bool is_linear;
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std::vector<u8> tmp_buffer;
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Data& regs;
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bool is_linear = false;
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Registers& regs;
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MemoryManager& memory_manager;
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MemoryManager& memory_manager;
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};
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};
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@ -51,7 +51,7 @@ public:
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struct {
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struct {
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INSERT_PADDING_WORDS(0x60);
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INSERT_PADDING_WORDS(0x60);
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Upload::Data upload;
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Upload::Registers upload;
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struct {
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struct {
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union {
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union {
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@ -131,7 +131,6 @@ public:
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BitField<30, 1, u32> linked_tsc;
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BitField<30, 1, u32> linked_tsc;
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BitField<0, 31, u32> grid_dim_x;
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BitField<0, 31, u32> grid_dim_x;
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union {
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union {
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BitField<0, 16, u32> grid_dim_y;
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BitField<0, 16, u32> grid_dim_y;
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BitField<16, 16, u32> grid_dim_z;
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BitField<16, 16, u32> grid_dim_z;
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@ -142,7 +141,6 @@ public:
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BitField<0, 16, u32> shared_alloc;
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BitField<0, 16, u32> shared_alloc;
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BitField<0, 31, u32> block_dim_x;
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BitField<0, 31, u32> block_dim_x;
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union {
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union {
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BitField<0, 16, u32> block_dim_y;
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BitField<0, 16, u32> block_dim_y;
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BitField<16, 16, u32> block_dim_z;
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BitField<16, 16, u32> block_dim_z;
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@ -47,7 +47,7 @@ public:
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struct {
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struct {
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INSERT_PADDING_WORDS(0x60);
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INSERT_PADDING_WORDS(0x60);
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Upload::Data upload;
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Upload::Registers upload;
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struct {
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struct {
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union {
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union {
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@ -588,7 +588,7 @@ public:
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INSERT_PADDING_WORDS(0x17);
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INSERT_PADDING_WORDS(0x17);
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Upload::Data upload;
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Upload::Registers upload;
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struct {
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struct {
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union {
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union {
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BitField<0, 1, u32> linear;
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BitField<0, 1, u32> linear;
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@ -70,13 +70,13 @@ public:
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static_assert(sizeof(Parameters) == 24, "Parameters has wrong size");
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static_assert(sizeof(Parameters) == 24, "Parameters has wrong size");
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enum class ComponentMode : u32 {
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enum class ComponentMode : u32 {
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SRC0 = 0,
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Src0 = 0,
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SRC1 = 1,
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Src1 = 1,
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SRC2 = 2,
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Src2 = 2,
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SRC3 = 3,
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Src3 = 3,
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CONST0 = 4,
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Const0 = 4,
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CONST1 = 5,
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Const1 = 5,
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ZERO = 6,
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Zero = 6,
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};
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};
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enum class CopyMode : u32 {
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enum class CopyMode : u32 {
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