vulkan: Add VK_EXT_vertex_input_dynamic_state support
Reduces the number of total pipelines generated on Vulkan. Tested on Super Smash Bros. Ultimate.
This commit is contained in:
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cb78a1b494
commit
ea038d6653
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@ -50,7 +50,7 @@ void RefreshXfbState(VideoCommon::TransformFeedbackState& state, const Maxwell&
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} // Anonymous namespace
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void FixedPipelineState::Refresh(Tegra::Engines::Maxwell3D& maxwell3d,
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bool has_extended_dynamic_state) {
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bool has_extended_dynamic_state, bool has_dynamic_vertex_input) {
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const Maxwell& regs = maxwell3d.regs;
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const std::array enabled_lut{
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regs.polygon_offset_point_enable,
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@ -60,7 +60,8 @@ void FixedPipelineState::Refresh(Tegra::Engines::Maxwell3D& maxwell3d,
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const u32 topology_index = static_cast<u32>(regs.draw.topology.Value());
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raw1 = 0;
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no_extended_dynamic_state.Assign(has_extended_dynamic_state ? 0 : 1);
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extended_dynamic_state.Assign(has_extended_dynamic_state ? 1 : 0);
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dynamic_vertex_input.Assign(has_dynamic_vertex_input ? 1 : 0);
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xfb_enabled.Assign(regs.tfb_enabled != 0);
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primitive_restart_enable.Assign(regs.primitive_restart.enabled != 0 ? 1 : 0);
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depth_bias_enable.Assign(enabled_lut[POLYGON_OFFSET_ENABLE_LUT[topology_index]] != 0 ? 1 : 0);
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@ -73,11 +74,11 @@ void FixedPipelineState::Refresh(Tegra::Engines::Maxwell3D& maxwell3d,
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tessellation_clockwise.Assign(regs.tess_mode.cw.Value());
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logic_op_enable.Assign(regs.logic_op.enable != 0 ? 1 : 0);
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logic_op.Assign(PackLogicOp(regs.logic_op.operation));
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rasterize_enable.Assign(regs.rasterize_enable != 0 ? 1 : 0);
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topology.Assign(regs.draw.topology);
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msaa_mode.Assign(regs.multisample_mode);
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raw2 = 0;
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rasterize_enable.Assign(regs.rasterize_enable != 0 ? 1 : 0);
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const auto test_func =
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regs.alpha_test_enabled != 0 ? regs.alpha_test_func : Maxwell::ComparisonOp::Always;
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alpha_test_func.Assign(PackComparisonOp(test_func));
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@ -93,24 +94,44 @@ void FixedPipelineState::Refresh(Tegra::Engines::Maxwell3D& maxwell3d,
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alpha_test_ref = Common::BitCast<u32>(regs.alpha_test_ref);
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point_size = Common::BitCast<u32>(regs.point_size);
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if (maxwell3d.dirty.flags[Dirty::InstanceDivisors]) {
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maxwell3d.dirty.flags[Dirty::InstanceDivisors] = false;
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for (size_t index = 0; index < Maxwell::NumVertexArrays; ++index) {
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const bool is_enabled = regs.instanced_arrays.IsInstancingEnabled(index);
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binding_divisors[index] = is_enabled ? regs.vertex_array[index].divisor : 0;
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}
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}
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if (maxwell3d.dirty.flags[Dirty::VertexAttributes]) {
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maxwell3d.dirty.flags[Dirty::VertexAttributes] = false;
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for (size_t index = 0; index < Maxwell::NumVertexAttributes; ++index) {
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const auto& input = regs.vertex_attrib_format[index];
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auto& attribute = attributes[index];
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attribute.raw = 0;
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attribute.enabled.Assign(input.IsConstant() ? 0 : 1);
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attribute.buffer.Assign(input.buffer);
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attribute.offset.Assign(input.offset);
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attribute.type.Assign(static_cast<u32>(input.type.Value()));
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attribute.size.Assign(static_cast<u32>(input.size.Value()));
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if (maxwell3d.dirty.flags[Dirty::VertexInput]) {
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if (has_dynamic_vertex_input) {
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// Dirty flag will be reset by the command buffer update
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static constexpr std::array LUT{
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0u, // Invalid
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1u, // SignedNorm
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1u, // UnsignedNorm
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2u, // SignedInt
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3u, // UnsignedInt
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1u, // UnsignedScaled
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1u, // SignedScaled
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1u, // Float
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};
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const auto& attrs = regs.vertex_attrib_format;
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attribute_types = 0;
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for (size_t i = 0; i < Maxwell::NumVertexAttributes; ++i) {
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const u32 mask = attrs[i].constant != 0 ? 0 : 3;
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const u32 type = LUT[static_cast<size_t>(attrs[i].type.Value())];
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attribute_types |= static_cast<u64>(type & mask) << (i * 2);
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}
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} else {
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maxwell3d.dirty.flags[Dirty::VertexInput] = false;
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enabled_divisors = 0;
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for (size_t index = 0; index < Maxwell::NumVertexArrays; ++index) {
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const bool is_enabled = regs.instanced_arrays.IsInstancingEnabled(index);
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binding_divisors[index] = is_enabled ? regs.vertex_array[index].divisor : 0;
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enabled_divisors |= (is_enabled ? u64{1} : 0) << index;
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}
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for (size_t index = 0; index < Maxwell::NumVertexAttributes; ++index) {
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const auto& input = regs.vertex_attrib_format[index];
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auto& attribute = attributes[index];
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attribute.raw = 0;
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attribute.enabled.Assign(input.IsConstant() ? 0 : 1);
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attribute.buffer.Assign(input.buffer);
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attribute.offset.Assign(input.offset);
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attribute.type.Assign(static_cast<u32>(input.type.Value()));
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attribute.size.Assign(static_cast<u32>(input.size.Value()));
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}
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}
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}
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if (maxwell3d.dirty.flags[Dirty::Blending]) {
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@ -126,10 +147,10 @@ void FixedPipelineState::Refresh(Tegra::Engines::Maxwell3D& maxwell3d,
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return static_cast<u16>(viewport.swizzle.raw);
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});
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}
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if (no_extended_dynamic_state != 0) {
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if (!extended_dynamic_state) {
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dynamic_state.Refresh(regs);
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}
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if (xfb_enabled != 0) {
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if (xfb_enabled) {
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RefreshXfbState(xfb_state, regs);
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}
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}
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@ -168,44 +168,51 @@ struct FixedPipelineState {
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union {
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u32 raw1;
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BitField<0, 1, u32> no_extended_dynamic_state;
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BitField<1, 1, u32> xfb_enabled;
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BitField<2, 1, u32> primitive_restart_enable;
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BitField<3, 1, u32> depth_bias_enable;
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BitField<4, 1, u32> depth_clamp_disabled;
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BitField<5, 1, u32> ndc_minus_one_to_one;
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BitField<6, 2, u32> polygon_mode;
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BitField<8, 5, u32> patch_control_points_minus_one;
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BitField<13, 2, u32> tessellation_primitive;
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BitField<15, 2, u32> tessellation_spacing;
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BitField<17, 1, u32> tessellation_clockwise;
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BitField<18, 1, u32> logic_op_enable;
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BitField<19, 4, u32> logic_op;
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BitField<23, 1, u32> rasterize_enable;
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BitField<0, 1, u32> extended_dynamic_state;
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BitField<1, 1, u32> dynamic_vertex_input;
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BitField<2, 1, u32> xfb_enabled;
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BitField<3, 1, u32> primitive_restart_enable;
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BitField<4, 1, u32> depth_bias_enable;
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BitField<5, 1, u32> depth_clamp_disabled;
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BitField<6, 1, u32> ndc_minus_one_to_one;
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BitField<7, 2, u32> polygon_mode;
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BitField<9, 5, u32> patch_control_points_minus_one;
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BitField<14, 2, u32> tessellation_primitive;
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BitField<16, 2, u32> tessellation_spacing;
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BitField<18, 1, u32> tessellation_clockwise;
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BitField<19, 1, u32> logic_op_enable;
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BitField<20, 4, u32> logic_op;
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BitField<24, 4, Maxwell::PrimitiveTopology> topology;
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BitField<28, 4, Tegra::Texture::MsaaMode> msaa_mode;
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};
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union {
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u32 raw2;
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BitField<0, 3, u32> alpha_test_func;
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BitField<3, 1, u32> early_z;
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BitField<4, 1, u32> depth_enabled;
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BitField<5, 5, u32> depth_format;
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BitField<10, 1, u32> y_negate;
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BitField<11, 1, u32> provoking_vertex_last;
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BitField<0, 1, u32> rasterize_enable;
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BitField<1, 3, u32> alpha_test_func;
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BitField<4, 1, u32> early_z;
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BitField<5, 1, u32> depth_enabled;
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BitField<6, 5, u32> depth_format;
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BitField<11, 1, u32> y_negate;
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BitField<12, 1, u32> provoking_vertex_last;
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};
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std::array<u8, Maxwell::NumRenderTargets> color_formats;
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u32 alpha_test_ref;
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u32 point_size;
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std::array<u32, Maxwell::NumVertexArrays> binding_divisors;
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std::array<VertexAttribute, Maxwell::NumVertexAttributes> attributes;
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std::array<BlendingAttachment, Maxwell::NumRenderTargets> attachments;
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std::array<u16, Maxwell::NumViewports> viewport_swizzles;
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union {
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u64 attribute_types; // Used with VK_EXT_vertex_input_dynamic_state
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u64 enabled_divisors;
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};
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std::array<VertexAttribute, Maxwell::NumVertexAttributes> attributes;
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std::array<u32, Maxwell::NumVertexArrays> binding_divisors;
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DynamicState dynamic_state;
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VideoCommon::TransformFeedbackState xfb_state;
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void Refresh(Tegra::Engines::Maxwell3D& maxwell3d, bool has_extended_dynamic_state);
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void Refresh(Tegra::Engines::Maxwell3D& maxwell3d, bool has_extended_dynamic_state,
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bool has_dynamic_vertex_input);
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size_t Hash() const noexcept;
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@ -216,16 +223,24 @@ struct FixedPipelineState {
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}
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size_t Size() const noexcept {
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if (xfb_enabled != 0) {
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if (xfb_enabled) {
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// When transform feedback is enabled, use the whole struct
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return sizeof(*this);
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} else if (no_extended_dynamic_state != 0) {
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// Dynamic state is enabled, we can enable more
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return offsetof(FixedPipelineState, xfb_state);
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} else {
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// No XFB, extended dynamic state enabled
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}
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if (dynamic_vertex_input) {
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// Exclude dynamic state and attributes
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return offsetof(FixedPipelineState, attributes);
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}
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if (extended_dynamic_state) {
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// Exclude dynamic state
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return offsetof(FixedPipelineState, dynamic_state);
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}
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// Default
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return offsetof(FixedPipelineState, xfb_state);
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}
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u32 DynamicAttributeType(size_t index) const noexcept {
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return (attribute_types >> (index * 2)) & 0b11;
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}
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};
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static_assert(std::has_unique_object_representations_v<FixedPipelineState>);
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@ -472,39 +472,65 @@ void GraphicsPipeline::ConfigureDraw() {
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void GraphicsPipeline::MakePipeline(VkRenderPass render_pass) {
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FixedPipelineState::DynamicState dynamic{};
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if (!device.IsExtExtendedDynamicStateSupported()) {
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if (key.state.extended_dynamic_state) {
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dynamic = key.state.dynamic_state;
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}
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static_vector<VkVertexInputBindingDescription, 32> vertex_bindings;
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static_vector<VkVertexInputBindingDivisorDescriptionEXT, 32> vertex_binding_divisors;
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for (size_t index = 0; index < Maxwell::NumVertexArrays; ++index) {
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const bool instanced = key.state.binding_divisors[index] != 0;
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const auto rate = instanced ? VK_VERTEX_INPUT_RATE_INSTANCE : VK_VERTEX_INPUT_RATE_VERTEX;
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vertex_bindings.push_back({
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.binding = static_cast<u32>(index),
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.stride = dynamic.vertex_strides[index],
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.inputRate = rate,
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});
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if (instanced) {
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vertex_binding_divisors.push_back({
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.binding = static_cast<u32>(index),
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.divisor = key.state.binding_divisors[index],
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static_vector<VkVertexInputAttributeDescription, 32> vertex_attributes;
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if (key.state.dynamic_vertex_input) {
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const auto& input_attributes = stage_infos[0].input_generics;
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for (size_t index = 0; index < key.state.attributes.size(); ++index) {
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const u32 type = key.state.DynamicAttributeType(index);
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if (!input_attributes[index].used || type == 0) {
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continue;
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}
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vertex_attributes.push_back({
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.location = static_cast<u32>(index),
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.binding = 0,
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.format = type == 1 ? VK_FORMAT_R32_SFLOAT
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: type == 2 ? VK_FORMAT_R32_SINT
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: VK_FORMAT_R32_UINT,
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.offset = 0,
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});
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}
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}
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static_vector<VkVertexInputAttributeDescription, 32> vertex_attributes;
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const auto& input_attributes = stage_infos[0].input_generics;
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for (size_t index = 0; index < key.state.attributes.size(); ++index) {
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const auto& attribute = key.state.attributes[index];
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if (!attribute.enabled || !input_attributes[index].used) {
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continue;
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if (!vertex_attributes.empty()) {
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vertex_bindings.push_back({
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.binding = 0,
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.stride = 4,
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.inputRate = VK_VERTEX_INPUT_RATE_VERTEX,
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});
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}
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} else {
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for (size_t index = 0; index < Maxwell::NumVertexArrays; ++index) {
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const bool instanced = key.state.binding_divisors[index] != 0;
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const auto rate =
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instanced ? VK_VERTEX_INPUT_RATE_INSTANCE : VK_VERTEX_INPUT_RATE_VERTEX;
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vertex_bindings.push_back({
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.binding = static_cast<u32>(index),
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.stride = dynamic.vertex_strides[index],
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.inputRate = rate,
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});
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if (instanced) {
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vertex_binding_divisors.push_back({
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.binding = static_cast<u32>(index),
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.divisor = key.state.binding_divisors[index],
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});
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}
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}
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const auto& input_attributes = stage_infos[0].input_generics;
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for (size_t index = 0; index < key.state.attributes.size(); ++index) {
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const auto& attribute = key.state.attributes[index];
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if (!attribute.enabled || !input_attributes[index].used) {
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continue;
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}
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vertex_attributes.push_back({
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.location = static_cast<u32>(index),
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.binding = attribute.buffer,
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.format = MaxwellToVK::VertexFormat(attribute.Type(), attribute.Size()),
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.offset = attribute.offset,
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});
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}
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vertex_attributes.push_back({
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.location = static_cast<u32>(index),
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.binding = attribute.buffer,
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.format = MaxwellToVK::VertexFormat(attribute.Type(), attribute.Size()),
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.offset = attribute.offset,
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});
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}
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VkPipelineVertexInputStateCreateInfo vertex_input_ci{
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.sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
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@ -545,27 +571,25 @@ void GraphicsPipeline::MakePipeline(VkRenderPass render_pass) {
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.flags = 0,
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.patchControlPoints = key.state.patch_control_points_minus_one.Value() + 1,
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};
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VkPipelineViewportStateCreateInfo viewport_ci{
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.sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
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.pNext = nullptr,
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.flags = 0,
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.viewportCount = Maxwell::NumViewports,
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.pViewports = nullptr,
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.scissorCount = Maxwell::NumViewports,
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.pScissors = nullptr,
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};
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std::array<VkViewportSwizzleNV, Maxwell::NumViewports> swizzles;
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std::ranges::transform(key.state.viewport_swizzles, swizzles.begin(), UnpackViewportSwizzle);
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VkPipelineViewportSwizzleStateCreateInfoNV swizzle_ci{
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const VkPipelineViewportSwizzleStateCreateInfoNV swizzle_ci{
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.sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_SWIZZLE_STATE_CREATE_INFO_NV,
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.pNext = nullptr,
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.flags = 0,
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.viewportCount = Maxwell::NumViewports,
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.pViewportSwizzles = swizzles.data(),
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};
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if (device.IsNvViewportSwizzleSupported()) {
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viewport_ci.pNext = &swizzle_ci;
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}
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const VkPipelineViewportStateCreateInfo viewport_ci{
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.sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
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.pNext = device.IsNvViewportSwizzleSupported() ? &swizzle_ci : nullptr,
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.flags = 0,
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.viewportCount = Maxwell::NumViewports,
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.pViewports = nullptr,
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.scissorCount = Maxwell::NumViewports,
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.pScissors = nullptr,
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};
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const VkPipelineRasterizationProvokingVertexStateCreateInfoEXT provoking_vertex{
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.sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_PROVOKING_VERTEX_STATE_CREATE_INFO_EXT,
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@ -660,13 +684,13 @@ void GraphicsPipeline::MakePipeline(VkRenderPass render_pass) {
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.pAttachments = cb_attachments.data(),
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.blendConstants = {},
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};
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static_vector<VkDynamicState, 17> dynamic_states{
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static_vector<VkDynamicState, 18> dynamic_states{
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VK_DYNAMIC_STATE_VIEWPORT, VK_DYNAMIC_STATE_SCISSOR,
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VK_DYNAMIC_STATE_DEPTH_BIAS, VK_DYNAMIC_STATE_BLEND_CONSTANTS,
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VK_DYNAMIC_STATE_DEPTH_BOUNDS, VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
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VK_DYNAMIC_STATE_STENCIL_WRITE_MASK, VK_DYNAMIC_STATE_STENCIL_REFERENCE,
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};
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if (device.IsExtExtendedDynamicStateSupported()) {
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if (key.state.extended_dynamic_state) {
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static constexpr std::array extended{
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VK_DYNAMIC_STATE_CULL_MODE_EXT,
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VK_DYNAMIC_STATE_FRONT_FACE_EXT,
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@ -678,6 +702,9 @@ void GraphicsPipeline::MakePipeline(VkRenderPass render_pass) {
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VK_DYNAMIC_STATE_STENCIL_TEST_ENABLE_EXT,
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VK_DYNAMIC_STATE_STENCIL_OP_EXT,
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};
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if (key.state.dynamic_vertex_input) {
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dynamic_states.push_back(VK_DYNAMIC_STATE_VERTEX_INPUT_EXT);
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}
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dynamic_states.insert(dynamic_states.end(), extended.begin(), extended.end());
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}
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const VkPipelineDynamicStateCreateInfo dynamic_state_ci{
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@ -109,6 +109,20 @@ static Shader::AttributeType CastAttributeType(const FixedPipelineState::VertexA
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return Shader::AttributeType::Float;
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}
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Shader::AttributeType AttributeType(const FixedPipelineState& state, size_t index) {
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switch (state.DynamicAttributeType(index)) {
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case 0:
|
||||
return Shader::AttributeType::Disabled;
|
||||
case 1:
|
||||
return Shader::AttributeType::Float;
|
||||
case 2:
|
||||
return Shader::AttributeType::SignedInt;
|
||||
case 3:
|
||||
return Shader::AttributeType::UnsignedInt;
|
||||
}
|
||||
return Shader::AttributeType::Disabled;
|
||||
}
|
||||
|
||||
Shader::RuntimeInfo MakeRuntimeInfo(const GraphicsPipelineCacheKey& key,
|
||||
const Shader::IR::Program& program) {
|
||||
Shader::RuntimeInfo info;
|
||||
|
@ -123,13 +137,19 @@ Shader::RuntimeInfo MakeRuntimeInfo(const GraphicsPipelineCacheKey& key,
|
|||
if (key.state.topology == Maxwell::PrimitiveTopology::Points) {
|
||||
info.fixed_state_point_size = point_size;
|
||||
}
|
||||
if (key.state.xfb_enabled != 0) {
|
||||
if (key.state.xfb_enabled) {
|
||||
info.xfb_varyings = VideoCommon::MakeTransformFeedbackVaryings(key.state.xfb_state);
|
||||
}
|
||||
info.convert_depth_mode = gl_ndc;
|
||||
}
|
||||
std::ranges::transform(key.state.attributes, info.generic_input_types.begin(),
|
||||
&CastAttributeType);
|
||||
if (key.state.dynamic_vertex_input) {
|
||||
for (size_t index = 0; index < Maxwell::NumVertexAttributes; ++index) {
|
||||
info.generic_input_types[index] = AttributeType(key.state, index);
|
||||
}
|
||||
} else {
|
||||
std::ranges::transform(key.state.attributes, info.generic_input_types.begin(),
|
||||
&CastAttributeType);
|
||||
}
|
||||
break;
|
||||
case Shader::Stage::TessellationEval:
|
||||
// We have to flip tessellation clockwise for some reason...
|
||||
|
@ -298,7 +318,8 @@ GraphicsPipeline* PipelineCache::CurrentGraphicsPipeline() {
|
|||
current_pipeline = nullptr;
|
||||
return nullptr;
|
||||
}
|
||||
graphics_key.state.Refresh(maxwell3d, device.IsExtExtendedDynamicStateSupported());
|
||||
graphics_key.state.Refresh(maxwell3d, device.IsExtExtendedDynamicStateSupported(),
|
||||
device.IsExtVertexInputDynamicStateSupported());
|
||||
|
||||
if (current_pipeline) {
|
||||
GraphicsPipeline* const next{current_pipeline->Next(graphics_key)};
|
||||
|
|
|
@ -551,6 +551,9 @@ void RasterizerVulkan::UpdateDynamicStates() {
|
|||
UpdateFrontFace(regs);
|
||||
UpdateStencilOp(regs);
|
||||
UpdateStencilTestEnable(regs);
|
||||
if (device.IsExtVertexInputDynamicStateSupported()) {
|
||||
UpdateVertexInput(regs);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -780,4 +783,57 @@ void RasterizerVulkan::UpdateStencilTestEnable(Tegra::Engines::Maxwell3D::Regs&
|
|||
});
|
||||
}
|
||||
|
||||
void RasterizerVulkan::UpdateVertexInput(Tegra::Engines::Maxwell3D::Regs& regs) {
|
||||
auto& dirty{maxwell3d.dirty.flags};
|
||||
if (!dirty[Dirty::VertexInput]) {
|
||||
return;
|
||||
}
|
||||
dirty[Dirty::VertexInput] = false;
|
||||
|
||||
boost::container::static_vector<VkVertexInputBindingDescription2EXT, 32> bindings;
|
||||
boost::container::static_vector<VkVertexInputAttributeDescription2EXT, 32> attributes;
|
||||
|
||||
for (size_t index = 0; index < Maxwell::NumVertexAttributes; ++index) {
|
||||
if (!dirty[Dirty::VertexAttribute0 + index]) {
|
||||
continue;
|
||||
}
|
||||
const Maxwell::VertexAttribute attribute{regs.vertex_attrib_format[index]};
|
||||
const u32 binding{attribute.buffer};
|
||||
dirty[Dirty::VertexAttribute0 + index] = false;
|
||||
dirty[Dirty::VertexBinding0 + static_cast<size_t>(binding)] = true;
|
||||
|
||||
attributes.push_back({
|
||||
.sType = VK_STRUCTURE_TYPE_VERTEX_INPUT_ATTRIBUTE_DESCRIPTION_2_EXT,
|
||||
.pNext = nullptr,
|
||||
.location = static_cast<u32>(index),
|
||||
.binding = binding,
|
||||
.format = attribute.IsConstant()
|
||||
? VK_FORMAT_A8B8G8R8_UNORM_PACK32
|
||||
: MaxwellToVK::VertexFormat(attribute.type, attribute.size),
|
||||
.offset = attribute.offset,
|
||||
});
|
||||
}
|
||||
for (size_t index = 0; index < Maxwell::NumVertexAttributes; ++index) {
|
||||
if (!dirty[Dirty::VertexBinding0 + index]) {
|
||||
continue;
|
||||
}
|
||||
dirty[Dirty::VertexBinding0 + index] = false;
|
||||
|
||||
const u32 binding{static_cast<u32>(index)};
|
||||
const auto& input_binding{regs.vertex_array[binding]};
|
||||
const bool is_instanced{regs.instanced_arrays.IsInstancingEnabled(binding)};
|
||||
bindings.push_back({
|
||||
.sType = VK_STRUCTURE_TYPE_VERTEX_INPUT_BINDING_DESCRIPTION_2_EXT,
|
||||
.pNext = nullptr,
|
||||
.binding = binding,
|
||||
.stride = input_binding.stride,
|
||||
.inputRate = is_instanced ? VK_VERTEX_INPUT_RATE_INSTANCE : VK_VERTEX_INPUT_RATE_VERTEX,
|
||||
.divisor = is_instanced ? input_binding.divisor : 1,
|
||||
});
|
||||
}
|
||||
scheduler.Record([bindings, attributes](vk::CommandBuffer cmdbuf) {
|
||||
cmdbuf.SetVertexInputEXT(bindings, attributes);
|
||||
});
|
||||
}
|
||||
|
||||
} // namespace Vulkan
|
||||
|
|
|
@ -135,6 +135,8 @@ private:
|
|||
void UpdateStencilOp(Tegra::Engines::Maxwell3D::Regs& regs);
|
||||
void UpdateStencilTestEnable(Tegra::Engines::Maxwell3D::Regs& regs);
|
||||
|
||||
void UpdateVertexInput(Tegra::Engines::Maxwell3D::Regs& regs);
|
||||
|
||||
Tegra::GPU& gpu;
|
||||
Tegra::MemoryManager& gpu_memory;
|
||||
Tegra::Engines::Maxwell3D& maxwell3d;
|
||||
|
|
|
@ -29,9 +29,10 @@ using Flags = Maxwell3D::DirtyState::Flags;
|
|||
|
||||
Flags MakeInvalidationFlags() {
|
||||
static constexpr int INVALIDATION_FLAGS[]{
|
||||
Viewports, Scissors, DepthBias, BlendConstants, DepthBounds,
|
||||
StencilProperties, CullMode, DepthBoundsEnable, DepthTestEnable, DepthWriteEnable,
|
||||
DepthCompareOp, FrontFace, StencilOp, StencilTestEnable, VertexBuffers,
|
||||
Viewports, Scissors, DepthBias, BlendConstants,
|
||||
DepthBounds, StencilProperties, CullMode, DepthBoundsEnable,
|
||||
DepthTestEnable, DepthWriteEnable, DepthCompareOp, FrontFace,
|
||||
StencilOp, StencilTestEnable, VertexBuffers, VertexInput,
|
||||
};
|
||||
Flags flags{};
|
||||
for (const int flag : INVALIDATION_FLAGS) {
|
||||
|
@ -40,6 +41,12 @@ Flags MakeInvalidationFlags() {
|
|||
for (int index = VertexBuffer0; index <= VertexBuffer31; ++index) {
|
||||
flags[index] = true;
|
||||
}
|
||||
for (int index = VertexAttribute0; index <= VertexAttribute31; ++index) {
|
||||
flags[index] = true;
|
||||
}
|
||||
for (int index = VertexBinding0; index <= VertexBinding31; ++index) {
|
||||
flags[index] = true;
|
||||
}
|
||||
return flags;
|
||||
}
|
||||
|
||||
|
@ -134,19 +141,6 @@ void SetupDirtyBlending(Tables& tables) {
|
|||
FillBlock(tables[0], OFF(independent_blend), NUM(independent_blend), Blending);
|
||||
}
|
||||
|
||||
void SetupDirtyInstanceDivisors(Tables& tables) {
|
||||
static constexpr size_t divisor_offset = 3;
|
||||
for (size_t index = 0; index < Regs::NumVertexArrays; ++index) {
|
||||
tables[0][OFF(instanced_arrays) + index] = InstanceDivisors;
|
||||
tables[0][OFF(vertex_array) + index * NUM(vertex_array[0]) + divisor_offset] =
|
||||
InstanceDivisors;
|
||||
}
|
||||
}
|
||||
|
||||
void SetupDirtyVertexAttributes(Tables& tables) {
|
||||
FillBlock(tables[0], OFF(vertex_attrib_format), NUM(vertex_attrib_format), VertexAttributes);
|
||||
}
|
||||
|
||||
void SetupDirtyViewportSwizzles(Tables& tables) {
|
||||
static constexpr size_t swizzle_offset = 6;
|
||||
for (size_t index = 0; index < Regs::NumViewports; ++index) {
|
||||
|
@ -154,11 +148,31 @@ void SetupDirtyViewportSwizzles(Tables& tables) {
|
|||
ViewportSwizzles;
|
||||
}
|
||||
}
|
||||
|
||||
void SetupDirtyVertexAttributes(Tables& tables) {
|
||||
for (size_t i = 0; i < Regs::NumVertexAttributes; ++i) {
|
||||
const size_t offset = OFF(vertex_attrib_format) + i * NUM(vertex_attrib_format[0]);
|
||||
FillBlock(tables[0], offset, NUM(vertex_attrib_format[0]), VertexAttribute0 + i);
|
||||
}
|
||||
FillBlock(tables[1], OFF(vertex_attrib_format), Regs::NumVertexAttributes, VertexInput);
|
||||
}
|
||||
|
||||
void SetupDirtyVertexBindings(Tables& tables) {
|
||||
// Do NOT include stride here, it's implicit in VertexBuffer
|
||||
static constexpr size_t divisor_offset = 3;
|
||||
for (size_t i = 0; i < Regs::NumVertexArrays; ++i) {
|
||||
const u8 flag = static_cast<u8>(VertexBinding0 + i);
|
||||
tables[0][OFF(instanced_arrays) + i] = VertexInput;
|
||||
tables[1][OFF(instanced_arrays) + i] = flag;
|
||||
tables[0][OFF(vertex_array) + i * NUM(vertex_array[0]) + divisor_offset] = VertexInput;
|
||||
tables[1][OFF(vertex_array) + i * NUM(vertex_array[0]) + divisor_offset] = flag;
|
||||
}
|
||||
}
|
||||
} // Anonymous namespace
|
||||
|
||||
StateTracker::StateTracker(Tegra::GPU& gpu)
|
||||
: flags{gpu.Maxwell3D().dirty.flags}, invalidation_flags{MakeInvalidationFlags()} {
|
||||
auto& tables = gpu.Maxwell3D().dirty.tables;
|
||||
auto& tables{gpu.Maxwell3D().dirty.tables};
|
||||
SetupDirtyFlags(tables);
|
||||
SetupDirtyViewports(tables);
|
||||
SetupDirtyScissors(tables);
|
||||
|
@ -175,9 +189,9 @@ StateTracker::StateTracker(Tegra::GPU& gpu)
|
|||
SetupDirtyStencilOp(tables);
|
||||
SetupDirtyStencilTestEnable(tables);
|
||||
SetupDirtyBlending(tables);
|
||||
SetupDirtyInstanceDivisors(tables);
|
||||
SetupDirtyVertexAttributes(tables);
|
||||
SetupDirtyViewportSwizzles(tables);
|
||||
SetupDirtyVertexAttributes(tables);
|
||||
SetupDirtyVertexBindings(tables);
|
||||
}
|
||||
|
||||
} // namespace Vulkan
|
||||
|
|
|
@ -19,6 +19,12 @@ namespace Dirty {
|
|||
enum : u8 {
|
||||
First = VideoCommon::Dirty::LastCommonEntry,
|
||||
|
||||
VertexInput,
|
||||
VertexAttribute0,
|
||||
VertexAttribute31 = VertexAttribute0 + 31,
|
||||
VertexBinding0,
|
||||
VertexBinding31 = VertexBinding0 + 31,
|
||||
|
||||
Viewports,
|
||||
Scissors,
|
||||
DepthBias,
|
||||
|
@ -36,8 +42,6 @@ enum : u8 {
|
|||
StencilTestEnable,
|
||||
|
||||
Blending,
|
||||
InstanceDivisors,
|
||||
VertexAttributes,
|
||||
ViewportSwizzles,
|
||||
|
||||
Last
|
||||
|
|
|
@ -239,6 +239,11 @@ public:
|
|||
return ext_extended_dynamic_state;
|
||||
}
|
||||
|
||||
/// Returns true if the device supports VK_EXT_vertex_input_dynamic_state.
|
||||
bool IsExtVertexInputDynamicStateSupported() const {
|
||||
return ext_vertex_input_dynamic_state;
|
||||
}
|
||||
|
||||
/// Returns true if the device supports VK_EXT_shader_stencil_export.
|
||||
bool IsExtShaderStencilExportSupported() const {
|
||||
return ext_shader_stencil_export;
|
||||
|
@ -349,6 +354,7 @@ private:
|
|||
bool ext_transform_feedback{}; ///< Support for VK_EXT_transform_feedback.
|
||||
bool ext_custom_border_color{}; ///< Support for VK_EXT_custom_border_color.
|
||||
bool ext_extended_dynamic_state{}; ///< Support for VK_EXT_extended_dynamic_state.
|
||||
bool ext_vertex_input_dynamic_state{}; ///< Support for VK_EXT_vertex_input_dynamic_state.
|
||||
bool ext_shader_stencil_export{}; ///< Support for VK_EXT_shader_stencil_export.
|
||||
bool ext_shader_atomic_int64{}; ///< Support for VK_KHR_shader_atomic_int64.
|
||||
bool ext_provoking_vertex{}; ///< Support for VK_EXT_provoking_vertex.
|
||||
|
|
|
@ -123,6 +123,7 @@ void Load(VkDevice device, DeviceDispatch& dld) noexcept {
|
|||
X(vkCmdSetPrimitiveTopologyEXT);
|
||||
X(vkCmdSetStencilOpEXT);
|
||||
X(vkCmdSetStencilTestEnableEXT);
|
||||
X(vkCmdSetVertexInputEXT);
|
||||
X(vkCmdResolveImage);
|
||||
X(vkCreateBuffer);
|
||||
X(vkCreateBufferView);
|
||||
|
|
|
@ -238,6 +238,7 @@ struct DeviceDispatch : InstanceDispatch {
|
|||
PFN_vkCmdSetPrimitiveTopologyEXT vkCmdSetPrimitiveTopologyEXT{};
|
||||
PFN_vkCmdSetStencilOpEXT vkCmdSetStencilOpEXT{};
|
||||
PFN_vkCmdSetStencilTestEnableEXT vkCmdSetStencilTestEnableEXT{};
|
||||
PFN_vkCmdSetVertexInputEXT vkCmdSetVertexInputEXT{};
|
||||
PFN_vkCmdResolveImage vkCmdResolveImage{};
|
||||
PFN_vkCreateBuffer vkCreateBuffer{};
|
||||
PFN_vkCreateBufferView vkCreateBufferView{};
|
||||
|
@ -1203,6 +1204,13 @@ public:
|
|||
dld->vkCmdSetStencilTestEnableEXT(handle, enable ? VK_TRUE : VK_FALSE);
|
||||
}
|
||||
|
||||
void SetVertexInputEXT(
|
||||
vk::Span<VkVertexInputBindingDescription2EXT> bindings,
|
||||
vk::Span<VkVertexInputAttributeDescription2EXT> attributes) const noexcept {
|
||||
dld->vkCmdSetVertexInputEXT(handle, bindings.size(), bindings.data(), attributes.size(),
|
||||
attributes.data());
|
||||
}
|
||||
|
||||
void BindTransformFeedbackBuffersEXT(u32 first, u32 count, const VkBuffer* buffers,
|
||||
const VkDeviceSize* offsets,
|
||||
const VkDeviceSize* sizes) const noexcept {
|
||||
|
|
Reference in New Issue