shader: Optimize NVN Fallthrough
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153a77efee
commit
ee61ec2c39
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@ -840,6 +840,9 @@ void EmitContext::DefineGlobalMemoryFunctions(const Info& info) {
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AddLabel();
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const size_t num_buffers{info.storage_buffers_descriptors.size()};
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for (size_t index = 0; index < num_buffers; ++index) {
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if (!info.nvn_buffer_used[index]) {
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continue;
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}
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const auto& ssbo{info.storage_buffers_descriptors[index]};
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const Id ssbo_addr_cbuf_offset{Const(ssbo.cbuf_offset / 8)};
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const Id ssbo_size_cbuf_offset{Const(ssbo.cbuf_offset / 4 + 2)};
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@ -88,17 +88,20 @@ void AddNVNStorageBuffers(IR::Program& program) {
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}()};
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auto& descs{program.info.storage_buffers_descriptors};
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for (u32 index = 0; index < num_buffers; ++index) {
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if (!program.info.nvn_buffer_used[index]) {
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continue;
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}
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const u32 offset{base + index * descriptor_size};
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const auto it{std::ranges::find(descs, offset, &StorageBufferDescriptor::cbuf_offset)};
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if (it != descs.end()) {
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it->is_written |= program.info.stores_global_memory;
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continue;
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}
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// Assume these are written for now
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descs.push_back({
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.cbuf_index = driver_cbuf,
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.cbuf_offset = offset,
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.count = 1,
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.is_written = true,
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.is_written = program.info.stores_global_memory,
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});
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}
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}
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@ -132,6 +132,30 @@ void SetPatch(Info& info, IR::Patch patch) {
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}
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}
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void CheckCBufNVN(Info& info, IR::Inst& inst) {
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const IR::Value cbuf_index{inst.Arg(0)};
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if (!cbuf_index.IsImmediate()) {
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info.nvn_buffer_used.set();
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return;
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}
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const u32 index{cbuf_index.U32()};
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if (index != 0) {
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return;
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}
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const IR::Value cbuf_offset{inst.Arg(1)};
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if (!cbuf_offset.IsImmediate()) {
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info.nvn_buffer_used.set();
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return;
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}
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const u32 offset{cbuf_offset.U32()};
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const u32 descriptor_size{0x10};
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const u32 upper_limit{info.nvn_buffer_base + descriptor_size * 16};
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if (offset >= info.nvn_buffer_base && offset < upper_limit) {
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const std::size_t nvn_index{(offset - info.nvn_buffer_base) / descriptor_size};
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info.nvn_buffer_used.set(nvn_index, true);
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}
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}
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void VisitUsages(Info& info, IR::Inst& inst) {
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switch (inst.GetOpcode()) {
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case IR::Opcode::CompositeConstructF16x2:
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@ -382,13 +406,6 @@ void VisitUsages(Info& info, IR::Inst& inst) {
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break;
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}
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switch (inst.GetOpcode()) {
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case IR::Opcode::LoadGlobalU8:
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case IR::Opcode::LoadGlobalS8:
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case IR::Opcode::LoadGlobalU16:
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case IR::Opcode::LoadGlobalS16:
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case IR::Opcode::LoadGlobal32:
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case IR::Opcode::LoadGlobal64:
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case IR::Opcode::LoadGlobal128:
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case IR::Opcode::WriteGlobalU8:
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case IR::Opcode::WriteGlobalS8:
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case IR::Opcode::WriteGlobalU16:
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@ -423,6 +440,15 @@ void VisitUsages(Info& info, IR::Inst& inst) {
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case IR::Opcode::GlobalAtomicMinF32x2:
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case IR::Opcode::GlobalAtomicMaxF16x2:
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case IR::Opcode::GlobalAtomicMaxF32x2:
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info.stores_global_memory = true;
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[[fallthrough]];
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case IR::Opcode::LoadGlobalU8:
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case IR::Opcode::LoadGlobalS8:
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case IR::Opcode::LoadGlobalU16:
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case IR::Opcode::LoadGlobalS16:
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case IR::Opcode::LoadGlobal32:
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case IR::Opcode::LoadGlobal64:
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case IR::Opcode::LoadGlobal128:
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info.uses_int64 = true;
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info.uses_global_memory = true;
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info.used_constant_buffer_types |= IR::Type::U32 | IR::Type::U32x2;
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@ -800,9 +826,27 @@ void VisitFpModifiers(Info& info, IR::Inst& inst) {
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}
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}
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void VisitCbufs(Info& info, IR::Inst& inst) {
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switch (inst.GetOpcode()) {
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case IR::Opcode::GetCbufU8:
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case IR::Opcode::GetCbufS8:
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case IR::Opcode::GetCbufU16:
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case IR::Opcode::GetCbufS16:
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case IR::Opcode::GetCbufU32:
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case IR::Opcode::GetCbufF32:
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case IR::Opcode::GetCbufU32x2: {
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CheckCBufNVN(info, inst);
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break;
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}
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default:
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break;
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}
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}
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void Visit(Info& info, IR::Inst& inst) {
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VisitUsages(info, inst);
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VisitFpModifiers(info, inst);
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VisitCbufs(info, inst);
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}
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void GatherInfoFromHeader(Environment& env, Info& info) {
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@ -839,6 +883,26 @@ void GatherInfoFromHeader(Environment& env, Info& info) {
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void CollectShaderInfoPass(Environment& env, IR::Program& program) {
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Info& info{program.info};
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const u32 base{[&] {
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switch (program.stage) {
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case Stage::VertexA:
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case Stage::VertexB:
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return 0x110u;
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case Stage::TessellationControl:
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return 0x210u;
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case Stage::TessellationEval:
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return 0x310u;
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case Stage::Geometry:
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return 0x410u;
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case Stage::Fragment:
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return 0x510u;
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case Stage::Compute:
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return 0x310u;
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}
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throw InvalidArgument("Invalid stage {}", program.stage);
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}()};
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info.nvn_buffer_base = base;
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for (IR::Block* const block : program.post_order_blocks) {
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for (IR::Inst& inst : block->Instructions()) {
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Visit(info, inst);
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@ -5,6 +5,7 @@
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#pragma once
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#include <array>
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#include <bitset>
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#include "common/common_types.h"
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#include "shader_recompiler/frontend/ir/type.h"
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@ -140,6 +141,7 @@ struct Info {
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bool stores_tess_level_outer{};
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bool stores_tess_level_inner{};
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bool stores_indexed_attributes{};
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bool stores_global_memory{};
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bool uses_fp16{};
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bool uses_fp64{};
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@ -180,6 +182,8 @@ struct Info {
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IR::Type used_storage_buffer_types{};
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u32 constant_buffer_mask{};
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u32 nvn_buffer_base{};
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std::bitset<16> nvn_buffer_used{};
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boost::container::static_vector<ConstantBufferDescriptor, MAX_CBUFS>
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constant_buffer_descriptors;
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