Respect vs output map
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a2024d7497
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@ -71,7 +71,7 @@ struct Regs {
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BitField<0, 24, u32> viewport_depth_range; // float24
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BitField<0, 24, u32> viewport_depth_range; // float24
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BitField<0, 24, u32> viewport_depth_far_plane; // float24
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BitField<0, 24, u32> viewport_depth_far_plane; // float24
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INSERT_PADDING_WORDS(0x1);
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BitField<0, 3, u32> vs_output_total;
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union VSOutputAttributes {
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union VSOutputAttributes {
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// Maps components of output vertex attributes to semantics
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// Maps components of output vertex attributes to semantics
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@ -1157,8 +1157,10 @@ struct Regs {
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}
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}
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} input_register_map;
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} input_register_map;
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// OUTMAP_MASK, 0x28E, CODETRANSFER_END
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BitField<0, 16, u32> output_mask;
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INSERT_PADDING_WORDS(0x3);
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// 0x28E, CODETRANSFER_END
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INSERT_PADDING_WORDS(0x2);
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struct {
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struct {
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enum Format : u32
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enum Format : u32
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@ -109,15 +109,23 @@ OutputVertex Run(UnitState<false>& state, const InputVertex& input, int num_attr
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OutputVertex ret;
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OutputVertex ret;
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// TODO(neobrain): Under some circumstances, up to 16 attributes may be output. We need to
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// TODO(neobrain): Under some circumstances, up to 16 attributes may be output. We need to
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// figure out what those circumstances are and enable the remaining outputs then.
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// figure out what those circumstances are and enable the remaining outputs then.
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for (int i = 0; i < 7; ++i) {
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unsigned index = 0;
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const auto& output_register_map = g_state.regs.vs_output_attributes[i]; // TODO: Don't hardcode VS here
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for (unsigned i = 0; i < 7; ++i) {
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if (index >= g_state.regs.vs_output_total)
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break;
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if ((g_state.regs.vs.output_mask & (1 << i)) == 0)
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continue;
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const auto& output_register_map = g_state.regs.vs_output_attributes[index]; // TODO: Don't hardcode VS here
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u32 semantics[4] = {
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u32 semantics[4] = {
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output_register_map.map_x, output_register_map.map_y,
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output_register_map.map_x, output_register_map.map_y,
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output_register_map.map_z, output_register_map.map_w
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output_register_map.map_z, output_register_map.map_w
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};
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};
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for (int comp = 0; comp < 4; ++comp) {
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for (unsigned comp = 0; comp < 4; ++comp) {
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float24* out = ((float24*)&ret) + semantics[comp];
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float24* out = ((float24*)&ret) + semantics[comp];
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if (semantics[comp] != Regs::VSOutputAttributes::INVALID) {
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if (semantics[comp] != Regs::VSOutputAttributes::INVALID) {
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*out = state.registers.output[i][comp];
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*out = state.registers.output[i][comp];
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@ -127,10 +135,12 @@ OutputVertex Run(UnitState<false>& state, const InputVertex& input, int num_attr
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memset(out, 0, sizeof(*out));
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memset(out, 0, sizeof(*out));
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}
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}
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}
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}
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index++;
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}
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}
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// The hardware takes the absolute and saturates vertex colors like this, *before* doing interpolation
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// The hardware takes the absolute and saturates vertex colors like this, *before* doing interpolation
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for (int i = 0; i < 4; ++i) {
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for (unsigned i = 0; i < 4; ++i) {
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ret.color[i] = float24::FromFloat32(
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ret.color[i] = float24::FromFloat32(
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std::fmin(std::fabs(ret.color[i].ToFloat32()), 1.0f));
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std::fmin(std::fabs(ret.color[i].ToFloat32()), 1.0f));
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}
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}
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