ba02d564f8
Video Core: initial Implementation of InstanceDraw Packaging
2019-09-19 11:41:27 -04:00
0526bf1895
shader_ir/warp: Implement SHFL
2019-09-17 17:44:07 -03:00
393cc3ef2f
Merge pull request #2851 from ReinUsesLisp/srgb
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renderer_opengl: Fix sRGB blits
2019-09-15 10:38:10 -04:00
b8b1747704
Merge pull request #2824 from ReinUsesLisp/mme
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Revert "Revert #2466 " and stub FirmwareCall 4
2019-09-15 06:17:04 -04:00
193bfefce4
maxwell_3d: Update firmware 4 call stub commentary
2019-09-14 22:51:18 -03:00
36abf67e79
shader/image: Implement SUATOM and fix SUST
2019-09-10 20:22:31 -03:00
78574746bd
renderer_opengl: Fix sRGB blits
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Removes the sRGB hack of tracking if a frame used an sRGB rendertarget
to apply at least once to blit the final texture as sRGB. Instead of
doing this apply sRGB if the presented image has sRGB.
Also enable sRGB by default on Maxwell3D registers as some games seem to
assume this.
2019-09-10 19:31:42 -03:00
34b2c60f95
Merge pull request #2823 from ReinUsesLisp/shr-clamp
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shader/shift: Implement SHR wrapped and clamped variants
2019-09-10 11:56:17 -04:00
c7ec7bc1f5
Merge pull request #2810 from ReinUsesLisp/mme-opt
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maxwell_3d: Avoid moving macro_params
2019-09-10 11:55:45 -04:00
6170337001
gl_rasterizer: Implement image bindings
2019-09-05 20:35:51 -03:00
3a450c1395
kepler_compute: Implement texture queries
2019-09-05 20:35:51 -03:00
5f309b88db
Revert "Revert #2466 " and stub FirmwareCall 4
2019-09-04 01:55:45 -03:00
77ef4fa907
shader/shift: Implement SHR wrapped and clamped variants
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Nvidia defaults to wrapped shifts, but this is undefined behaviour on
OpenGL's spec. Explicitly mask/clamp according to what the guest shader
requires.
2019-09-04 01:55:24 -03:00
701dedcfad
maxwell_3d: Avoid moving macro_params
2019-09-04 01:55:01 -03:00
81fbc5370d
Merge pull request #2812 from ReinUsesLisp/f2i-selector
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shader_ir/conversion: Implement F2I and F2F F16 selector
2019-09-03 22:35:33 -04:00
d4f33b822b
Merge pull request #2811 from ReinUsesLisp/fsetp-fix
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float_set_predicate: Add missing negation bit for the second operand
2019-09-03 22:34:34 -04:00
137d165672
Merge pull request #2826 from ReinUsesLisp/macro-binding
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maxwell_3d: Fix macro binding cursor
2019-09-03 22:32:42 -04:00
50b5bb44a0
Merge pull request #2765 from FernandoS27/dma-fix
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MaxwellDMA: Fixes, corrections and relaxations.
2019-09-01 13:13:05 -04:00
52a41f482f
maxwell_3d: Fix macro binding cursor
2019-09-01 05:01:11 -03:00
4d4f9cc104
video_core: Silent miscellaneous warnings ( #2820 )
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* texture_cache/surface_params: Remove unused local variable
* rasterizer_interface: Add missing documentation commentary
* maxwell_dma: Remove unused rasterizer reference
* video_core/gpu: Sort member declaration order to silent -Wreorder warning
* fermi_2d: Remove unused MemoryManager reference
* video_core: Silent unused variable warnings
* buffer_cache: Silent -Wreorder warnings
* kepler_memory: Remove unused MemoryManager reference
* gl_texture_cache: Add missing override
* buffer_cache: Add missing include
* shader/decode: Remove unused variables
2019-08-30 14:08:00 -04:00
e3534700d7
shader_ir/conversion: Split int and float selector and implement F2F H1
2019-08-28 16:09:33 -03:00
b13fbc25b8
shader_ir/conversion: Implement F2I F16 Ra.H1
2019-08-27 23:40:40 -03:00
6207751b00
float_set_predicate: Add missing negation bit for the second operand
2019-08-27 21:57:43 -03:00
4e35177e23
shader_ir: Implement VOTE
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Implement VOTE using Nvidia's intrinsics. Documentation about these can
be found here
https://developer.nvidia.com/reading-between-threads-shader-intrinsics
Instead of using portable ARB instructions I opted to use Nvidia
intrinsics because these are the closest we have to how Tegra X1
hardware renders.
To stub VOTE on non-Nvidia drivers (including nouveau) this commit
simulates a GPU with a warp size of one, returning what is meaningful
for the instruction being emulated:
* anyThreadNV(value) -> value
* allThreadsNV(value) -> value
* allThreadsEqualNV(value) -> true
ballotARB, also known as "uint64_t(activeThreadsNV())", emits
VOTE.ANY Rd, PT, PT;
on nouveau's compiler. This doesn't match exactly to Nvidia's code
VOTE.ALL Rd, PT, PT;
Which is emulated with activeThreadsNV() by this commit. In theory this
shouldn't really matter since .ANY, .ALL and .EQ affect the predicates
(set to PT on those cases) and not the registers.
2019-08-21 14:50:38 -03:00
cedc1aab4a
Merge pull request #2753 from FernandoS27/float-convert
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Shader_Ir: Implement F16 Variants of F2F, F2I, I2F.
2019-08-21 10:27:57 -04:00
2ff8044806
shader_ir: Implement NOP
2019-08-04 03:02:55 -03:00
52f54c728d
Merge pull request #2592 from FernandoS27/sync1
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Implement GPU Synchronization Mechanisms & Correct NVFlinger
2019-07-26 14:26:44 -04:00
a452ff983d
MaxwellDMA: Fixes, corrections and relaxations.
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This commit fixes offsets on Linear -> Tiled copies, corrects z pos
fortiled->linear copies, corrects bytes_per_pixel calculation in tiled
-> linear copies and relaxes some limitations set by latest dma fixes
refactors.
2019-07-25 20:41:42 -04:00
31e8a61527
Merge pull request #2743 from FernandoS27/surpress-assert
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Downgrade and suppress a series of GPU asserts and debug messages.
2019-07-25 12:34:36 -04:00
9be9600bdc
Merge pull request #2704 from FernandoS27/conditional
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maxwell3d: Implement Conditional Rendering
2019-07-24 17:07:57 -04:00
f601f25bcc
Merge pull request #2734 from ReinUsesLisp/compute-shaders
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gl_rasterizer: Implement compute shaders
2019-07-22 11:12:55 -04:00
27e10e0442
Merge pull request #2735 from FernandoS27/pipeline-rework
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Rework Dirty Flags in GPU Pipeline, Optimize CBData and Redo Clearing mechanism
2019-07-21 00:59:52 -04:00
11f4e739bd
Shader_Ir: Implement F16 Variants of F2F, F2I, I2F.
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This commit takes care of implementing the F16 Variants of the
conversion instructions and makes sure conversions are done.
2019-07-20 17:38:25 -04:00
7a35178ee2
Maxwell3D: Reorganize and address feedback
2019-07-20 10:18:35 -04:00
6c4985edc9
shader/half_set_predicate: Implement missing HSETP2 variants
2019-07-19 22:20:47 -03:00
3a3fee5abf
MaxwellDMA/KeplerCopy: Downgrade DMA log message to Trace.
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This log was just to know which games used DMA. It's no longer
important.
2019-07-18 08:31:38 -04:00
4be61013a1
GL_State: Feedback and fixes
2019-07-17 17:29:56 -04:00
5ad889f6fd
Maxwell3D: Address Feedback
2019-07-17 17:29:55 -04:00
8cdbfe69b1
GL_Rasterizer: Corrections to Clearing.
2019-07-17 17:29:54 -04:00
0ff4a5fa39
Maxwell3D: Correct marking dirtiness on CB upload
2019-07-17 17:29:53 -04:00
fec32fed18
GL_Rasterizer: Rework RenderTarget/DepthBuffer clearing
2019-07-17 17:29:52 -04:00
a081dea8ab
Maxwell3D: Implement State Dirty Flags.
2019-07-17 17:29:51 -04:00
0d3db58657
Maxwell3D: Rework CBData Upload
2019-07-17 17:29:50 -04:00
f2e7b29c14
Maxwell3D: Rework the dirty system to be more consistant and scaleable
2019-07-17 17:29:49 -04:00
e42bcf2314
maxwell3d: Implement Conditional Rendering
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Conditional Rendering takes care of conditionaly clearing or drawing
depending on a set of queries. This PR implements the query checks to
stablish if things can be rendered or not.
2019-07-17 17:13:19 -04:00
725ba6cf63
gl_rasterizer: Implement compute shaders
2019-07-15 17:38:25 -03:00
1bdb59fc6e
Merge pull request #2695 from ReinUsesLisp/layer-viewport
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gl_shader_decompiler: Implement gl_ViewportIndex and gl_Layer in vertex shaders
2019-07-15 16:28:07 -04:00
3477b92289
Merge pull request #2675 from ReinUsesLisp/opengl-buffer-cache
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buffer_cache: Implement a generic buffer cache and its OpenGL backend
2019-07-14 19:03:43 -04:00
0ec9da2f9f
Merge pull request #2692 from ReinUsesLisp/tlds-f16
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shader/texture: Add F16 support for TLDS
2019-07-14 08:44:38 -04:00
8a6fc529a9
shader_ir: Implement BRX & BRA.CC
2019-07-09 08:14:37 -04:00
c9d886c84e
gl_shader_decompiler: Implement gl_ViewportIndex and gl_Layer in vertex shaders
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This commit implements gl_ViewportIndex and gl_Layer in vertex and
geometry shaders. In the case it's used in a vertex shader, it requires
ARB_shader_viewport_layer_array. This extension is available on AMD and
Nvidia devices (mesa and proprietary drivers), but not available on
Intel on any platform. At the moment of writing this description I don't
know if this is a hardware limitation or a driver limitation.
In the case that ARB_shader_viewport_layer_array is not available,
writes to these registers on a vertex shader are ignored, with the
appropriate logging.
2019-07-07 20:42:55 -03:00
d0966b9f7c
shader/texture: Add F16 support for TLDS
2019-07-07 16:05:56 -03:00
7ecf64257a
gl_rasterizer: Minor style changes
2019-07-06 00:37:55 -03:00
82b829625b
video_core: Implement GPU side Syncpoints
2019-07-05 15:49:11 -04:00
4d63f97945
shader_bytecode: Include missing <array>
2019-06-24 01:51:02 -03:00
082740d34d
surface: Correct format S8Z24
2019-06-20 21:38:34 -03:00
7232a1ed16
decoders: correct block calculation
2019-06-20 21:38:34 -03:00
cb728797b0
fermi2d: Correct Origin Mode
2019-06-20 21:38:34 -03:00
175aa343ff
texture_cache: Fermi2D reform and implement View Mirage
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This also does some fixes on compressed textures reinterpret and on the
Fermi2D engine in general.
2019-06-20 21:38:33 -03:00
06c4ce8645
shader: Decode SUST and implement backing image functionality
2019-06-20 21:38:33 -03:00
b8c75a845b
maxwell_3d: Partially implement texture buffers as 1D textures
2019-06-20 21:36:12 -03:00
4e81fc8296
shader: Implement texture buffers
2019-06-20 21:36:12 -03:00
d267948a73
texture_cache: loose TryReconstructSurface when accurate GPU is not on.
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Also corrects some asserts.
2019-06-20 21:36:12 -03:00
6bd034eae9
engine_upload: Addapt to new Texture Cache
2019-06-20 21:36:12 -03:00
345e73f2fe
video_core: Use un-shifted block sizes to avoid integer divisions
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Instead of storing all block width, height and depths in their shifted
form:
block_width = 1U << block_shift;
Store them like they are provided by the emulated hardware (their
block_shift form). This way we can avoid doing the costly
Common::AlignUp operation to align texture sizes and drop CPU integer
divisions with bitwise logic (defined in Common::AlignBits).
2019-06-20 21:36:12 -03:00
c7b5c245e1
Merge pull request #2562 from ReinUsesLisp/split-cbuf-upload
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video_core/engines: Move ConstBufferInfo out of Maxwell3D
2019-06-17 22:35:04 -04:00
528c15051c
kepler_compute: Use std::array for cbuf info
2019-06-07 20:36:22 -03:00
17d5fb6d06
kepler_compute: Fix block_dim_x encoding
2019-06-07 20:35:46 -03:00
2f2a61887a
video_core/engines: Move ConstBufferInfo out of Maxwell3D
2019-06-07 19:47:15 -03:00
a32c52b1d8
shader_bytecode: Mark EXIT as flow instruction
2019-06-04 12:18:35 -04:00
75e7b45d69
shader/memory: Implement ST (generic memory)
2019-05-20 22:41:53 -03:00
f78ef617b6
shader/memory: Implement LD (generic memory)
2019-05-20 22:38:59 -03:00
d49efbfb4a
Merge pull request #2441 from ReinUsesLisp/al2p
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shader: Implement AL2P and ALD.PHYS
2019-05-19 14:02:58 -04:00
b54bd3f018
Merge pull request #2472 from FernandoS27/tic
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maxwell_3d: reduce severity of different component formats assert.
2019-05-19 15:04:47 +01:00
3bd5f01240
Merge pull request #2469 from lioncash/copyable
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video_core/engines/maxwell_3d: Add is_trivially_copyable_v check for Regs
2019-05-19 15:02:17 +01:00
a6ed792ac4
Merge pull request #2470 from lioncash/ranged-for
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video_core/engines/maxwell_3d: Simplify for loops into ranged for loops within InitializeRegisterDefaults()
2019-05-19 09:01:19 -05:00
fc975e9021
maxwell_3d: reduce sevirity of different component formats assert.
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This was reduced due to happening on most games and at such constant
rate that it affected performance heavily for the end user. In general,
we are well aware of the assert and an implementation is already
planned.
2019-05-14 17:12:54 -04:00
b01cce716e
video_core/engines/engine_upload: Amend constructor initializer list order
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Silences a -Wreorder warning.
2019-05-14 13:43:28 -04:00
9b6d993e52
video_core/engines/engine_upload: Default destructor in the cpp file
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Avoids inlining destruction logic where applicable, and also makes
forward declarations not cause unexpected compilation errors depending
on where the State class is used.
2019-05-14 13:41:41 -04:00
ec1c69258a
video_core/engines/engine_upload: Remove unnecessary const on parameters in function declarations
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These only apply in the definition of the function. They can be omitted
from the declaration.
2019-05-14 13:40:09 -04:00
0f83c8dffa
video_core/engines/engine_upload: Remove unnecessary includes
2019-05-14 13:39:04 -04:00
5db1b54b58
video_core/engines/maxwell3d: Get rid of three magic values in CallMethod()
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We can use the named constant instead of using 32 directly.
2019-05-14 09:02:47 -04:00
48ce5880a0
video_core/engines/maxwell_3d: Simplify for loops into ranged for loops within InitializeRegisterDefaults()
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Lessens the amount of code that needs to be read, and gets rid of the
need to introduce an indexing variable. Instead, we just operate on the
objects directly.
2019-05-14 08:53:19 -04:00
c212fc9b2c
video_core/engines/maxwell_3d: Add is_trivially_copyable_v check for Regs
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std::memset is used to clear the entire register structure, which
requires that the Regs struct be trivially copyable (otherwise undefined
behavior is invoked). This prevents the case where a non-trivial type is
potentially added to the struct.
2019-05-14 08:47:56 -04:00
c27b81cb85
Merge pull request #2429 from FernandoS27/compute
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Corrections and Implementation on GPU Engines
2019-05-09 13:19:22 -04:00
d4df803b2b
shader_ir/other: Implement IPA.IDX
2019-05-02 21:46:37 -03:00
71aa9d0877
shader_ir/memory: Implement physical input attributes
2019-05-02 21:46:25 -03:00
bd81a03d9d
gl_shader_decompiler: Declare all possible varyings on physical attribute usage
2019-05-02 21:46:25 -03:00
7632a7d6d2
shader_bytecode: Add AL2P decoding
2019-05-02 21:46:25 -03:00
e64c41efe8
Refactors and name corrections.
2019-05-01 15:31:39 -04:00
c52233ec8b
Merge pull request #2322 from ReinUsesLisp/wswitch
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video_core: Silent -Wswitch warnings
2019-04-28 22:24:58 -04:00
b3118ee316
Fixes and Corrections to DMA Engine
2019-04-23 15:28:18 -04:00
f1e5314f1a
Add Swizzle Parameters to the DMA engine
2019-04-23 11:21:00 -04:00
e140e2ebc6
Add Documentation Headers to all the GPU Engines
2019-04-23 08:44:52 -04:00
021d28c9b8
Corrections and styling
2019-04-23 08:02:24 -04:00
701ce1c9d0
Implement Maxwell3D Data Upload
2019-04-22 19:27:36 -04:00
e4ff140b99
Introduce skeleton of the GPU Compute Engine.
2019-04-22 19:05:43 -04:00
a91d3fc639
Revamp Kepler Memory to use a subegine to manage uploads
2019-04-22 18:50:56 -04:00
68b707711a
Merge pull request #2411 from FernandoS27/unsafe-gpu
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GPU Manager: Implement ReadBlockUnsafe and WriteBlockUnsafe
2019-04-22 17:09:00 -04:00
01100f8afd
Merge pull request #2400 from FernandoS27/corret-kepler-mem
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Implement Kepler Memory on both Linear and BlockLinear.
2019-04-22 16:47:05 -04:00
Fernando Sahmkow
ReinUsesLisp
bunnei
Hexagon12
Sebastian Valle
Lioncash