132 lines
4.8 KiB
C++
132 lines
4.8 KiB
C++
// Copyright 2018 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "common/assert.h"
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#include "common/common_types.h"
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#include "video_core/engines/shader_bytecode.h"
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#include "video_core/shader/shader_ir.h"
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namespace VideoCommon::Shader {
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using Tegra::Shader::Instruction;
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using Tegra::Shader::OpCode;
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using Tegra::Shader::SubOp;
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u32 ShaderIR::DecodeArithmetic(BasicBlock& bb, u32 pc) {
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const Instruction instr = {program_code[pc]};
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const auto opcode = OpCode::Decode(instr);
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Node op_a = GetRegister(instr.gpr8);
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Node op_b = [&]() -> Node {
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if (instr.is_b_imm) {
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return GetImmediate19(instr);
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} else if (instr.is_b_gpr) {
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return GetRegister(instr.gpr20);
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} else {
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return GetConstBuffer(instr.cbuf34.index, instr.cbuf34.offset);
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}
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}();
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switch (opcode->get().GetId()) {
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case OpCode::Id::MOV_C:
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case OpCode::Id::MOV_R: {
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// MOV does not have neither 'abs' nor 'neg' bits.
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SetRegister(bb, instr.gpr0, op_b);
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break;
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}
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case OpCode::Id::FMUL_C:
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case OpCode::Id::FMUL_R:
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case OpCode::Id::FMUL_IMM: {
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// FMUL does not have 'abs' bits and only the second operand has a 'neg' bit.
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UNIMPLEMENTED_IF_MSG(instr.fmul.tab5cb8_2 != 0, "FMUL tab5cb8_2({}) is not implemented",
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instr.fmul.tab5cb8_2.Value());
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UNIMPLEMENTED_IF_MSG(
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instr.fmul.tab5c68_0 != 1, "FMUL tab5cb8_0({}) is not implemented",
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instr.fmul.tab5c68_0.Value()); // SMO typical sends 1 here which seems to be the default
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UNIMPLEMENTED_IF_MSG(instr.generates_cc,
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"Condition codes generation in FMUL is not implemented");
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op_b = GetOperandAbsNegFloat(op_b, false, instr.fmul.negate_b);
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// TODO(Rodrigo): Should precise be used when there's a postfactor?
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Node value = Operation(OperationCode::FMul, PRECISE, op_a, op_b);
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if (instr.fmul.postfactor != 0) {
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auto postfactor = static_cast<s32>(instr.fmul.postfactor);
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// Postfactor encoded as 3-bit 1's complement in instruction, interpreted with below
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// logic.
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if (postfactor >= 4) {
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postfactor = 7 - postfactor;
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} else {
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postfactor = 0 - postfactor;
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}
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if (postfactor > 0) {
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value = Operation(OperationCode::FMul, NO_PRECISE, value,
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Immediate(static_cast<f32>(1 << postfactor)));
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} else {
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value = Operation(OperationCode::FDiv, NO_PRECISE, value,
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Immediate(static_cast<f32>(1 << -postfactor)));
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}
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}
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value = GetSaturatedFloat(value, instr.alu.saturate_d);
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SetRegister(bb, instr.gpr0, value);
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break;
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}
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case OpCode::Id::FADD_C:
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case OpCode::Id::FADD_R:
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case OpCode::Id::FADD_IMM: {
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UNIMPLEMENTED_IF_MSG(instr.generates_cc,
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"Condition codes generation in FADD is not implemented");
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op_a = GetOperandAbsNegFloat(op_a, instr.alu.abs_a, instr.alu.negate_a);
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op_b = GetOperandAbsNegFloat(op_b, instr.alu.abs_b, instr.alu.negate_b);
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Node value = Operation(OperationCode::FAdd, PRECISE, op_a, op_b);
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value = GetSaturatedFloat(value, instr.alu.saturate_d);
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SetRegister(bb, instr.gpr0, value);
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break;
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}
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case OpCode::Id::MUFU: {
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op_a = GetOperandAbsNegFloat(op_a, instr.alu.abs_a, instr.alu.negate_a);
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Node value = [&]() {
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switch (instr.sub_op) {
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case SubOp::Cos:
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return Operation(OperationCode::FCos, PRECISE, op_a);
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case SubOp::Sin:
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return Operation(OperationCode::FSin, PRECISE, op_a);
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case SubOp::Ex2:
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return Operation(OperationCode::FExp2, PRECISE, op_a);
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case SubOp::Lg2:
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return Operation(OperationCode::FLog2, PRECISE, op_a);
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case SubOp::Rcp:
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return Operation(OperationCode::FDiv, PRECISE, Immediate(1.0f), op_a);
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case SubOp::Rsq:
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return Operation(OperationCode::FInverseSqrt, PRECISE, op_a);
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case SubOp::Sqrt:
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return Operation(OperationCode::FSqrt, PRECISE, op_a);
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default:
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UNIMPLEMENTED_MSG("Unhandled MUFU sub op={0:x}",
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static_cast<unsigned>(instr.sub_op.Value()));
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}
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}();
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value = GetSaturatedFloat(value, instr.alu.saturate_d);
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SetRegister(bb, instr.gpr0, value);
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break;
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}
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default:
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UNIMPLEMENTED_MSG("Unhandled arithmetic instruction: {}", opcode->get().GetName());
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}
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return pc;
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}
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} // namespace VideoCommon::Shader
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