shader_decode: Implement ST_A
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e3f1233ce1
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0c049e0a21
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@ -52,6 +52,36 @@ u32 ShaderIR::DecodeMemory(BasicBlock& bb, u32 pc) {
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}
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break;
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}
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case OpCode::Id::ST_A: {
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UNIMPLEMENTED_IF_MSG(instr.gpr8.Value() != Register::ZeroIndex,
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"Indirect attribute loads are not supported");
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UNIMPLEMENTED_IF_MSG((instr.attribute.fmt20.immediate.Value() % sizeof(u32)) != 0,
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"Unaligned attribute loads are not supported");
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u64 next_element = instr.attribute.fmt20.element;
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auto next_index = static_cast<u64>(instr.attribute.fmt20.index.Value());
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const auto StoreNextElement = [&](u32 reg_offset) {
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const auto dest = GetOutputAttribute(static_cast<Attribute::Index>(next_index),
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next_element, GetRegister(instr.gpr39));
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const auto src = GetRegister(instr.gpr0.Value() + reg_offset);
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bb.push_back(Operation(OperationCode::Assign, dest, src));
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// Load the next attribute element into the following register. If the element
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// to load goes beyond the vec4 size, load the first element of the next
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// attribute.
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next_element = (next_element + 1) % 4;
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next_index = next_index + (next_element == 0 ? 1 : 0);
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};
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const u32 num_words = static_cast<u32>(instr.attribute.fmt20.size.Value()) + 1;
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for (u32 reg_offset = 0; reg_offset < num_words; ++reg_offset) {
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StoreNextElement(reg_offset);
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}
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break;
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}
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default:
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UNIMPLEMENTED_MSG("Unhandled memory instruction: {}", opcode->get().GetName());
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}
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