shader: Implement FLO
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e038928616
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103b9da4f7
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@ -64,6 +64,7 @@ add_library(shader_recompiler STATIC
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frontend/maxwell/translate/impl/common_encoding.h
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frontend/maxwell/translate/impl/common_encoding.h
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frontend/maxwell/translate/impl/common_funcs.cpp
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frontend/maxwell/translate/impl/common_funcs.cpp
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frontend/maxwell/translate/impl/common_funcs.h
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frontend/maxwell/translate/impl/common_funcs.h
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frontend/maxwell/translate/impl/find_leading_one.cpp
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frontend/maxwell/translate/impl/floating_point_add.cpp
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frontend/maxwell/translate/impl/floating_point_add.cpp
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frontend/maxwell/translate/impl/floating_point_conversion_integer.cpp
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frontend/maxwell/translate/impl/floating_point_conversion_integer.cpp
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frontend/maxwell/translate/impl/floating_point_fused_multiply_add.cpp
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frontend/maxwell/translate/impl/floating_point_fused_multiply_add.cpp
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@ -229,7 +229,9 @@ Id EmitBitFieldSExtract(EmitContext& ctx, Id base, Id offset, Id count);
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Id EmitBitFieldUExtract(EmitContext& ctx, Id base, Id offset, Id count);
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Id EmitBitFieldUExtract(EmitContext& ctx, Id base, Id offset, Id count);
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Id EmitBitReverse32(EmitContext& ctx, Id value);
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Id EmitBitReverse32(EmitContext& ctx, Id value);
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Id EmitBitCount32(EmitContext& ctx, Id value);
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Id EmitBitCount32(EmitContext& ctx, Id value);
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Id EmitBitwiseNot32(EmitContext& ctx, Id a);
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Id EmitBitwiseNot32(EmitContext& ctx, Id value);
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Id EmitFindSMsb32(EmitContext& ctx, Id value);
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Id EmitFindUMsb32(EmitContext& ctx, Id value);
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Id EmitSMin32(EmitContext& ctx, Id a, Id b);
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Id EmitSMin32(EmitContext& ctx, Id a, Id b);
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Id EmitUMin32(EmitContext& ctx, Id a, Id b);
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Id EmitUMin32(EmitContext& ctx, Id a, Id b);
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Id EmitSMax32(EmitContext& ctx, Id a, Id b);
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Id EmitSMax32(EmitContext& ctx, Id a, Id b);
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@ -110,8 +110,16 @@ Id EmitBitCount32(EmitContext& ctx, Id value) {
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return ctx.OpBitCount(ctx.U32[1], value);
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return ctx.OpBitCount(ctx.U32[1], value);
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}
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}
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Id EmitBitwiseNot32(EmitContext& ctx, Id a) {
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Id EmitBitwiseNot32(EmitContext& ctx, Id value) {
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return ctx.OpNot(ctx.U32[1], a);
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return ctx.OpNot(ctx.U32[1], value);
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}
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Id EmitFindSMsb32(EmitContext& ctx, Id value) {
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return ctx.OpFindSMsb(ctx.U32[1], value);
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}
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Id EmitFindUMsb32(EmitContext& ctx, Id value) {
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return ctx.OpFindUMsb(ctx.U32[1], value);
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}
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}
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Id EmitSMin32(EmitContext& ctx, Id a, Id b) {
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Id EmitSMin32(EmitContext& ctx, Id a, Id b) {
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@ -812,8 +812,16 @@ U32 IREmitter::BitCount(const U32& value) {
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return Inst<U32>(Opcode::BitCount32, value);
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return Inst<U32>(Opcode::BitCount32, value);
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}
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}
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U32 IREmitter::BitwiseNot(const U32& a) {
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U32 IREmitter::BitwiseNot(const U32& value) {
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return Inst<U32>(Opcode::BitwiseNot32, a);
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return Inst<U32>(Opcode::BitwiseNot32, value);
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}
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U32 IREmitter::FindSMsb(const U32& value) {
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return Inst<U32>(Opcode::FindSMsb32, value);
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}
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U32 IREmitter::FindUMsb(const U32& value) {
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return Inst<U32>(Opcode::FindUMsb32, value);
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}
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}
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U32 IREmitter::SMin(const U32& a, const U32& b) {
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U32 IREmitter::SMin(const U32& a, const U32& b) {
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@ -161,8 +161,10 @@ public:
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bool is_signed);
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bool is_signed);
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[[nodiscard]] U32 BitReverse(const U32& value);
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[[nodiscard]] U32 BitReverse(const U32& value);
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[[nodiscard]] U32 BitCount(const U32& value);
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[[nodiscard]] U32 BitCount(const U32& value);
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[[nodiscard]] U32 BitwiseNot(const U32& a);
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[[nodiscard]] U32 BitwiseNot(const U32& value);
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[[nodiscard]] U32 FindSMsb(const U32& value);
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[[nodiscard]] U32 FindUMsb(const U32& value);
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[[nodiscard]] U32 SMin(const U32& a, const U32& b);
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[[nodiscard]] U32 SMin(const U32& a, const U32& b);
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[[nodiscard]] U32 UMin(const U32& a, const U32& b);
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[[nodiscard]] U32 UMin(const U32& a, const U32& b);
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[[nodiscard]] U32 SMax(const U32& a, const U32& b);
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[[nodiscard]] U32 SMax(const U32& a, const U32& b);
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@ -235,6 +235,8 @@ OPCODE(BitReverse32, U32, U32,
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OPCODE(BitCount32, U32, U32, )
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OPCODE(BitCount32, U32, U32, )
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OPCODE(BitwiseNot32, U32, U32, )
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OPCODE(BitwiseNot32, U32, U32, )
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OPCODE(FindSMsb32, U32, U32, )
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OPCODE(FindUMsb32, U32, U32, )
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OPCODE(SMin32, U32, U32, U32, )
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OPCODE(SMin32, U32, U32, U32, )
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OPCODE(UMin32, U32, U32, U32, )
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OPCODE(UMin32, U32, U32, U32, )
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OPCODE(SMax32, U32, U32, U32, )
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OPCODE(SMax32, U32, U32, U32, )
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@ -0,0 +1,46 @@
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// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "common/bit_field.h"
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#include "common/common_types.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
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namespace Shader::Maxwell {
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namespace {
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void FLO(TranslatorVisitor& v, u64 insn, const IR::U32& src) {
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union {
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u64 insn;
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BitField<0, 8, IR::Reg> dest_reg;
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BitField<40, 1, u64> tilde;
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BitField<41, 1, u64> shift;
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BitField<48, 1, u64> is_signed;
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} const flo{insn};
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const bool invert{flo.tilde != 0};
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const bool is_signed{flo.is_signed != 0};
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const bool shift_op{flo.shift != 0};
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const IR::U32 operand{invert ? v.ir.BitwiseNot(src) : src};
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const IR::U32 find_result{is_signed ? v.ir.FindSMsb(operand) : v.ir.FindUMsb(operand)};
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const IR::U1 find_fail{v.ir.IEqual(find_result, v.ir.Imm32(-1))};
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const IR::U32 offset{v.ir.Imm32(31)};
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const IR::U32 success_result{shift_op ? IR::U32{v.ir.ISub(offset, find_result)} : find_result};
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const IR::U32 result{v.ir.Select(find_fail, find_result, success_result)};
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v.X(flo.dest_reg, result);
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}
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} // Anonymous namespace
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void TranslatorVisitor::FLO_reg(u64 insn) {
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FLO(*this, insn, GetReg20(insn));
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}
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void TranslatorVisitor::FLO_cbuf(u64 insn) {
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FLO(*this, insn, GetCbuf(insn));
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}
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void TranslatorVisitor::FLO_imm(u64 insn) {
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FLO(*this, insn, GetImm20(insn));
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}
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} // namespace Shader::Maxwell
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@ -217,18 +217,6 @@ void TranslatorVisitor::FCMP_imm(u64) {
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ThrowNotImplemented(Opcode::FCMP_imm);
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ThrowNotImplemented(Opcode::FCMP_imm);
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}
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}
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void TranslatorVisitor::FLO_reg(u64) {
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ThrowNotImplemented(Opcode::FLO_reg);
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}
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void TranslatorVisitor::FLO_cbuf(u64) {
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ThrowNotImplemented(Opcode::FLO_cbuf);
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}
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void TranslatorVisitor::FLO_imm(u64) {
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ThrowNotImplemented(Opcode::FLO_imm);
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}
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void TranslatorVisitor::FMNMX_reg(u64) {
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void TranslatorVisitor::FMNMX_reg(u64) {
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ThrowNotImplemented(Opcode::FMNMX_reg);
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ThrowNotImplemented(Opcode::FMNMX_reg);
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}
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}
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