GPU: Make the SetShader macro call do the same as the real macro's code.
It'll now set the CB_SIZE, CB_ADDRESS and CB_BIND registers when it's called. Presumably this SetShader function is binding the constant shader uniforms to buffer 1 (c1[]).
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@ -84,7 +84,7 @@ void Maxwell3D::SetShader(const std::vector<u32>& parameters) {
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/**
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* Parameters description:
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* [0] = Shader Program.
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* [1] = Unknown.
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* [1] = Unknown, presumably the shader id.
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* [2] = Offset to the start of the shader, after the 0x30 bytes header.
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* [3] = Shader Type.
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* [4] = Const Buffer Address >> 8.
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@ -100,6 +100,24 @@ void Maxwell3D::SetShader(const std::vector<u32>& parameters) {
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shader.type = shader_type;
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shader.address = address;
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shader.cb_address = cb_address;
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// Perform the same operations as the real macro code.
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// TODO(Subv): Early exit if register 0xD1C + shader_program contains the same as params[1].
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auto& shader_regs = regs.shader_config[static_cast<size_t>(shader_program)];
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shader_regs.start_id = address;
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// TODO(Subv): Write params[1] to register 0xD1C + shader_program.
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// TODO(Subv): Write params[2] to register 0xD22 + shader_program.
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// Note: This value is hardcoded in the macro's code.
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static constexpr u32 DefaultCBSize = 0x10000;
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regs.const_buffer.cb_size = DefaultCBSize;
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regs.const_buffer.cb_address_high = cb_address >> 32;
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regs.const_buffer.cb_address_low = cb_address & 0xFFFFFFFF;
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// Write a hardcoded 0x11 to CB_BIND, this binds the current const buffer to buffer c1[] in the
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// shader. It's likely that these are the constants for the shader.
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regs.cb_bind[static_cast<size_t>(shader_type)].valid.Assign(1);
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regs.cb_bind[static_cast<size_t>(shader_type)].index.Assign(1);
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}
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} // namespace Engines
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@ -35,8 +35,10 @@ public:
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struct Regs {
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static constexpr size_t NUM_REGS = 0xE36;
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static constexpr size_t NumCBData = 16;
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static constexpr size_t NumVertexArrays = 32;
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static constexpr size_t MaxShaderProgram = 6;
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static constexpr size_t MaxShaderType = 5;
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enum class QueryMode : u32 {
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Write = 0,
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@ -136,7 +138,27 @@ public:
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INSERT_PADDING_WORDS(9);
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} shader_config[MaxShaderProgram];
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INSERT_PADDING_WORDS(0x5D0);
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INSERT_PADDING_WORDS(0x8C);
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struct {
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u32 cb_size;
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u32 cb_address_high;
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u32 cb_address_low;
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u32 cb_pos;
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u32 cb_data[NumCBData];
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} const_buffer;
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INSERT_PADDING_WORDS(0x74);
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struct {
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union {
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BitField<0, 1, u32> valid;
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BitField<4, 5, u32> index;
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};
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INSERT_PADDING_WORDS(7);
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} cb_bind[MaxShaderType];
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INSERT_PADDING_WORDS(0x494);
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struct {
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u32 set_shader_call;
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@ -161,7 +183,7 @@ public:
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std::array<ShaderInfo, Regs::MaxShaderProgram> shaders;
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};
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State state;
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State state{};
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private:
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MemoryManager& memory_manager;
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@ -194,6 +216,7 @@ ASSERT_REG_POSITION(query, 0x6C0);
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ASSERT_REG_POSITION(vertex_array[0], 0x700);
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ASSERT_REG_POSITION(vertex_array_limit[0], 0x7C0);
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ASSERT_REG_POSITION(shader_config[0], 0x800);
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ASSERT_REG_POSITION(const_buffer, 0x8E0);
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ASSERT_REG_POSITION(set_shader, 0xE24);
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#undef ASSERT_REG_POSITION
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