Replace old FragmentHeader for the new Header
This commit is contained in:
parent
e926757c8f
commit
2b48cfd44b
|
@ -5,8 +5,8 @@
|
|||
#pragma once
|
||||
|
||||
#include "common/bit_field.h"
|
||||
#include "common/common_types.h"
|
||||
#include "common/common_funcs.h"
|
||||
#include "common/common_types.h"
|
||||
|
||||
namespace Tegra::Shader {
|
||||
|
||||
|
@ -72,7 +72,7 @@ struct Header {
|
|||
INSERT_PADDING_BYTES(2); // OmapSystemValuesC
|
||||
INSERT_PADDING_BYTES(5); // OmapFixedFncTexture[10]
|
||||
INSERT_PADDING_BYTES(1); // OmapReserved
|
||||
} ps;
|
||||
} vtg;
|
||||
|
||||
struct {
|
||||
INSERT_PADDING_BYTES(3); // ImapSystemValuesA
|
||||
|
@ -82,14 +82,20 @@ struct Header {
|
|||
INSERT_PADDING_BYTES(2); // ImapSystemValuesC
|
||||
INSERT_PADDING_BYTES(10); // ImapFixedFncTexture[10]
|
||||
INSERT_PADDING_BYTES(2); // ImapReserved
|
||||
INSERT_PADDING_BYTES(4); // OmapTarget[8]
|
||||
union {
|
||||
BitField<0, 1, u32> omap_sample_mask;
|
||||
BitField<1, 1, u32> omap_depth;
|
||||
BitField<2, 30, u32> omap_reserved;
|
||||
struct {
|
||||
u32 target;
|
||||
union {
|
||||
BitField<0, 1, u32> sample_mask;
|
||||
BitField<1, 1, u32> depth;
|
||||
BitField<2, 30, u32> reserved;
|
||||
};
|
||||
} omap;
|
||||
} vtg;
|
||||
} sph;
|
||||
bool IsColorComponentOutputEnabled(u32 render_target, u32 component) const {
|
||||
const u32 bit = render_target * 4 + component;
|
||||
return omap.target & (1 << bit);
|
||||
}
|
||||
} ps;
|
||||
};
|
||||
};
|
||||
|
||||
static_assert(sizeof(Header) == 0x50, "Incorrect structure size");
|
||||
|
|
|
@ -689,23 +689,6 @@ public:
|
|||
}
|
||||
|
||||
private:
|
||||
// Shader program header for a Fragment Shader.
|
||||
struct FragmentHeader {
|
||||
INSERT_PADDING_WORDS(5);
|
||||
INSERT_PADDING_WORDS(13);
|
||||
u32 enabled_color_outputs;
|
||||
union {
|
||||
BitField<0, 1, u32> writes_samplemask;
|
||||
BitField<1, 1, u32> writes_depth;
|
||||
};
|
||||
|
||||
bool IsColorComponentOutputEnabled(u32 render_target, u32 component) const {
|
||||
const u32 bit = render_target * 4 + component;
|
||||
return enabled_color_outputs & (1 << bit);
|
||||
}
|
||||
};
|
||||
static_assert(sizeof(FragmentHeader) == PROGRAM_HEADER_SIZE, "FragmentHeader size is wrong");
|
||||
|
||||
/// Gets the Subroutine object corresponding to the specified address.
|
||||
const Subroutine& GetSubroutine(u32 begin, u32 end) const {
|
||||
const auto iter = subroutines.find(Subroutine{begin, end, suffix});
|
||||
|
@ -1011,10 +994,8 @@ private:
|
|||
/// Writes the output values from a fragment shader to the corresponding GLSL output variables.
|
||||
void EmitFragmentOutputsWrite() {
|
||||
ASSERT(stage == Maxwell3D::Regs::ShaderStage::Fragment);
|
||||
FragmentHeader header;
|
||||
std::memcpy(&header, program_code.data(), PROGRAM_HEADER_SIZE);
|
||||
|
||||
ASSERT_MSG(header.writes_samplemask == 0, "Samplemask write is unimplemented");
|
||||
ASSERT_MSG(header.ps.omap.sample_mask == 0, "Samplemask write is unimplemented");
|
||||
|
||||
// Write the color outputs using the data in the shader registers, disabled
|
||||
// rendertargets/components are skipped in the register assignment.
|
||||
|
@ -1023,7 +1004,7 @@ private:
|
|||
++render_target) {
|
||||
// TODO(Subv): Figure out how dual-source blending is configured in the Switch.
|
||||
for (u32 component = 0; component < 4; ++component) {
|
||||
if (header.IsColorComponentOutputEnabled(render_target, component)) {
|
||||
if (header.ps.IsColorComponentOutputEnabled(render_target, component)) {
|
||||
shader.AddLine(fmt::format("FragColor{}[{}] = {};", render_target, component,
|
||||
regs.GetRegisterAsFloat(current_reg)));
|
||||
++current_reg;
|
||||
|
@ -1031,7 +1012,7 @@ private:
|
|||
}
|
||||
}
|
||||
|
||||
if (header.writes_depth) {
|
||||
if (header.ps.omap.depth) {
|
||||
// The depth output is always 2 registers after the last color output, and current_reg
|
||||
// already contains one past the last color register.
|
||||
|
||||
|
|
Reference in New Issue