GPU: Added a function to retrieve the active textures for a shader stage.
TODO: A shader may not use all of these textures at the same time, shader analysis should be performed to determine which textures are actually sampled.
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@ -174,53 +174,13 @@ void Maxwell3D::ProcessQueryGet() {
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void Maxwell3D::DrawArrays() {
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LOG_WARNING(HW_GPU, "Game requested a DrawArrays, ignoring");
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if (Tegra::g_debug_context) {
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Tegra::g_debug_context->OnEvent(Tegra::DebugContext::Event::IncomingPrimitiveBatch, nullptr);
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}
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auto& fragment_shader = state.shader_stages[static_cast<size_t>(Regs::ShaderStage::Fragment)];
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auto& tex_info_buffer = fragment_shader.const_buffers[regs.tex_cb_index];
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ASSERT(tex_info_buffer.enabled && tex_info_buffer.address != 0);
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GPUVAddr tic_base_address = regs.tic.TICAddress();
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GPUVAddr tex_info_buffer_end = tex_info_buffer.address + tex_info_buffer.size;
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for (GPUVAddr current_texture = tex_info_buffer.address + 0x20;
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current_texture < tex_info_buffer_end; current_texture += 4) {
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Texture::TextureHandle tex_info{
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Memory::Read32(memory_manager.PhysicalToVirtualAddress(current_texture))};
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if (tex_info.tic_id != 0 || tex_info.tsc_id != 0) {
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GPUVAddr tic_address_gpu =
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tic_base_address + tex_info.tic_id * sizeof(Texture::TICEntry);
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VAddr tic_address_cpu = memory_manager.PhysicalToVirtualAddress(tic_address_gpu);
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Texture::TICEntry tic_entry;
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Memory::ReadBlock(tic_address_cpu, &tic_entry, sizeof(Texture::TICEntry));
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auto r_type = tic_entry.r_type.Value();
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auto g_type = tic_entry.g_type.Value();
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auto b_type = tic_entry.b_type.Value();
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auto a_type = tic_entry.a_type.Value();
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// TODO(Subv): Different data types for separate components are not supported
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ASSERT(r_type == g_type && r_type == b_type && r_type == a_type);
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auto format = tic_entry.format.Value();
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auto texture = Texture::UnswizzleTexture(
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memory_manager.PhysicalToVirtualAddress(tic_entry.Address()),
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tic_entry.format.Value(), tic_entry.Width(), tic_entry.Height());
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LOG_CRITICAL(HW_GPU,
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"Fragment shader using texture TIC %08X TSC %08X at address %016" PRIX64,
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tex_info.tic_id.Value(), tex_info.tsc_id.Value(), tic_entry.Address());
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}
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Tegra::g_debug_context->OnEvent(Tegra::DebugContext::Event::IncomingPrimitiveBatch,
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nullptr);
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}
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if (Tegra::g_debug_context) {
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Tegra::g_debug_context->OnEvent(Tegra::DebugContext::Event::FinishedPrimitiveBatch, nullptr);
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Tegra::g_debug_context->OnEvent(Tegra::DebugContext::Event::FinishedPrimitiveBatch,
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nullptr);
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}
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}
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@ -332,5 +292,50 @@ void Maxwell3D::ProcessCBData(u32 value) {
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regs.const_buffer.cb_pos = regs.const_buffer.cb_pos + 4;
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}
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std::vector<Texture::TICEntry> Maxwell3D::GetStageTextures(Regs::ShaderStage stage) {
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std::vector<Texture::TICEntry> textures;
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auto& fragment_shader = state.shader_stages[static_cast<size_t>(stage)];
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auto& tex_info_buffer = fragment_shader.const_buffers[regs.tex_cb_index];
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ASSERT(tex_info_buffer.enabled && tex_info_buffer.address != 0);
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GPUVAddr tic_base_address = regs.tic.TICAddress();
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GPUVAddr tex_info_buffer_end = tex_info_buffer.address + tex_info_buffer.size;
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// Offset into the texture constbuffer where the texture info begins.
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static constexpr size_t TextureInfoOffset = 0x20;
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for (GPUVAddr current_texture = tex_info_buffer.address + TextureInfoOffset;
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current_texture < tex_info_buffer_end; current_texture += 4) {
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Texture::TextureHandle tex_info{
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Memory::Read32(memory_manager.PhysicalToVirtualAddress(current_texture))};
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if (tex_info.tic_id != 0 || tex_info.tsc_id != 0) {
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GPUVAddr tic_address_gpu =
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tic_base_address + tex_info.tic_id * sizeof(Texture::TICEntry);
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VAddr tic_address_cpu = memory_manager.PhysicalToVirtualAddress(tic_address_gpu);
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Texture::TICEntry tic_entry;
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Memory::ReadBlock(tic_address_cpu, &tic_entry, sizeof(Texture::TICEntry));
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auto r_type = tic_entry.r_type.Value();
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auto g_type = tic_entry.g_type.Value();
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auto b_type = tic_entry.b_type.Value();
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auto a_type = tic_entry.a_type.Value();
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// TODO(Subv): Different data types for separate components are not supported
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ASSERT(r_type == g_type && r_type == b_type && r_type == a_type);
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auto format = tic_entry.format.Value();
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textures.push_back(tic_entry);
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}
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}
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return textures;
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}
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} // namespace Engines
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} // namespace Tegra
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@ -12,6 +12,7 @@
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#include "common/common_funcs.h"
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#include "common/common_types.h"
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#include "video_core/memory_manager.h"
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#include "video_core/textures/texture.h"
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namespace Tegra {
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namespace Engines {
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@ -21,12 +22,6 @@ public:
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explicit Maxwell3D(MemoryManager& memory_manager);
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~Maxwell3D() = default;
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/// Write the value to the register identified by method.
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void WriteReg(u32 method, u32 value, u32 remaining_params);
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/// Uploads the code for a GPU macro program associated with the specified entry.
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void SubmitMacroCode(u32 entry, std::vector<u32> code);
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/// Register structure of the Maxwell3D engine.
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/// TODO(Subv): This structure will need to be made bigger as more registers are discovered.
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struct Regs {
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@ -430,6 +425,15 @@ public:
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State state{};
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/// Write the value to the register identified by method.
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void WriteReg(u32 method, u32 value, u32 remaining_params);
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/// Uploads the code for a GPU macro program associated with the specified entry.
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void SubmitMacroCode(u32 entry, std::vector<u32> code);
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/// Returns a list of enabled textures for the specified shader stage.
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std::vector<Texture::TICEntry> GetStageTextures(Regs::ShaderStage stage);
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private:
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MemoryManager& memory_manager;
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