yuzu-emu
/
yuzu-mainline
Archived
1
0
Fork 0
Code

shader: Implement LOP CC

This commit is contained in:
ReinUsesLisp 2021-04-11 19:16:47 -03:00 committed by ameerj
parent 5c61e860e4
commit 2ed80f6b1e
3 changed files with 29 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/shader_recompiler/backend/spirv/emit_spirv.h
View File

@ -280,9 +280,9 @@ Id EmitShiftRightLogical32(EmitContext& ctx, Id base, Id shift);
Id EmitShiftRightLogical64(EmitContext& ctx, Id base, Id shift);
Id EmitShiftRightArithmetic32(EmitContext& ctx, Id base, Id shift);
Id EmitShiftRightArithmetic64(EmitContext& ctx, Id base, Id shift);
Id EmitBitwiseAnd32(EmitContext& ctx, Id a, Id b);
Id EmitBitwiseOr32(EmitContext& ctx, Id a, Id b);
Id EmitBitwiseXor32(EmitContext& ctx, Id a, Id b);
Id EmitBitwiseAnd32(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
Id EmitBitwiseOr32(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
Id EmitBitwiseXor32(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
Id EmitBitFieldInsert(EmitContext& ctx, Id base, Id insert, Id offset, Id count);
Id EmitBitFieldSExtract(EmitContext& ctx, IR::Inst* inst, Id base, Id offset, Id count);
Id EmitBitFieldUExtract(EmitContext& ctx, IR::Inst* inst, Id base, Id offset, Id count);

21
src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
View File

@ -111,16 +111,25 @@ Id EmitShiftRightArithmetic64(EmitContext& ctx, Id base, Id shift) {
return ctx.OpShiftRightArithmetic(ctx.U64, base, shift);
}
Id EmitBitwiseAnd32(EmitContext& ctx, Id a, Id b) {
return ctx.OpBitwiseAnd(ctx.U32[1], a, b);
Id EmitBitwiseAnd32(EmitContext& ctx, IR::Inst* inst, Id a, Id b) {
const Id result{ctx.OpBitwiseAnd(ctx.U32[1], a, b)};
SetZeroFlag(ctx, inst, result);
SetSignFlag(ctx, inst, result);
return result;
}
Id EmitBitwiseOr32(EmitContext& ctx, Id a, Id b) {
return ctx.OpBitwiseOr(ctx.U32[1], a, b);
Id EmitBitwiseOr32(EmitContext& ctx, IR::Inst* inst, Id a, Id b) {
const Id result{ctx.OpBitwiseOr(ctx.U32[1], a, b)};
SetZeroFlag(ctx, inst, result);
SetSignFlag(ctx, inst, result);
return result;
}
Id EmitBitwiseXor32(EmitContext& ctx, Id a, Id b) {
return ctx.OpBitwiseXor(ctx.U32[1], a, b);
Id EmitBitwiseXor32(EmitContext& ctx, IR::Inst* inst, Id a, Id b) {
const Id result{ctx.OpBitwiseXor(ctx.U32[1], a, b)};
SetZeroFlag(ctx, inst, result);
SetSignFlag(ctx, inst, result);
return result;
}
Id EmitBitFieldInsert(EmitContext& ctx, Id base, Id insert, Id offset, Id count) {

14
src/shader_recompiler/frontend/maxwell/translate/impl/logic_operation.cpp
View File

@ -44,9 +44,6 @@ void LOP(TranslatorVisitor& v, u64 insn, IR::U32 op_b, bool x, bool cc, bool inv
if (x) {
throw NotImplementedException("X");
}
if (cc) {
throw NotImplementedException("CC");
}
IR::U32 op_a{v.X(lop.src_reg)};
if (inv_a != 0) {
op_a = v.ir.BitwiseNot(op_a);
@ -60,6 +57,17 @@ void LOP(TranslatorVisitor& v, u64 insn, IR::U32 op_b, bool x, bool cc, bool inv
const IR::U1 pred_result{PredicateOperation(v.ir, result, *pred_op)};
v.ir.SetPred(dest_pred, pred_result);
}
if (cc) {
if (bit_op == LogicalOp::PASS_B) {
v.SetZFlag(v.ir.IEqual(result, v.ir.Imm32(0)));
v.SetSFlag(v.ir.ILessThan(result, v.ir.Imm32(0), true));
} else {
v.SetZFlag(v.ir.GetZeroFromOp(result));
v.SetSFlag(v.ir.GetSignFromOp(result));
}
v.ResetCFlag();
v.ResetOFlag();
}
v.X(lop.dest_reg, result);
}