glasm: Implement FSWZADD
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3da7b98d37
commit
36d040da70
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@ -281,7 +281,8 @@ void SetupOptions(const IR::Program& program, const Profile& profile, std::strin
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if (info.uses_atomic_f16x2_add || info.uses_atomic_f16x2_min || info.uses_atomic_f16x2_max) {
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if (info.uses_atomic_f16x2_add || info.uses_atomic_f16x2_min || info.uses_atomic_f16x2_max) {
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header += "OPTION NV_shader_atomic_fp16_vector;";
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header += "OPTION NV_shader_atomic_fp16_vector;";
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}
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}
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if (info.uses_subgroup_invocation_id || info.uses_subgroup_mask || info.uses_subgroup_vote) {
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if (info.uses_subgroup_invocation_id || info.uses_subgroup_mask || info.uses_subgroup_vote ||
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info.uses_fswzadd) {
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header += "OPTION NV_shader_thread_group;";
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header += "OPTION NV_shader_thread_group;";
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}
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}
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if (info.uses_subgroup_shuffles) {
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if (info.uses_subgroup_shuffles) {
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@ -416,12 +417,25 @@ std::string EmitGLASM(const Profile& profile, IR::Program& program, Bindings& bi
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if (program.local_memory_size > 0) {
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if (program.local_memory_size > 0) {
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header += fmt::format("lmem[{}],", program.local_memory_size);
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header += fmt::format("lmem[{}],", program.local_memory_size);
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}
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}
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if (program.info.uses_fswzadd) {
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header += "FSWZA[4],FSWZB[4],";
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}
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header += "RC;"
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header += "RC;"
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"LONG TEMP ";
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"LONG TEMP ";
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for (size_t index = 0; index < ctx.reg_alloc.NumUsedLongRegisters(); ++index) {
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for (size_t index = 0; index < ctx.reg_alloc.NumUsedLongRegisters(); ++index) {
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header += fmt::format("D{},", index);
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header += fmt::format("D{},", index);
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}
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}
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header += "DC;";
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header += "DC;";
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if (program.info.uses_fswzadd) {
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header += "MOV.F FSWZA[0],-1;"
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"MOV.F FSWZA[1],1;"
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"MOV.F FSWZA[2],-1;"
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"MOV.F FSWZA[3],0;"
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"MOV.F FSWZB[0],-1;"
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"MOV.F FSWZB[1],-1;"
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"MOV.F FSWZB[2],1;"
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"MOV.F FSWZB[3],-1;";
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}
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ctx.code.insert(0, header);
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ctx.code.insert(0, header);
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ctx.code += "END";
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ctx.code += "END";
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return ctx.code;
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return ctx.code;
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@ -616,7 +616,8 @@ void EmitShuffleDown(EmitContext& ctx, IR::Inst& inst, ScalarU32 value, ScalarU3
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const IR::Value& clamp, const IR::Value& segmentation_mask);
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const IR::Value& clamp, const IR::Value& segmentation_mask);
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void EmitShuffleButterfly(EmitContext& ctx, IR::Inst& inst, ScalarU32 value, ScalarU32 index,
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void EmitShuffleButterfly(EmitContext& ctx, IR::Inst& inst, ScalarU32 value, ScalarU32 index,
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const IR::Value& clamp, const IR::Value& segmentation_mask);
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const IR::Value& clamp, const IR::Value& segmentation_mask);
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void EmitFSwizzleAdd(EmitContext& ctx, ScalarF32 op_a, ScalarF32 op_b, ScalarU32 swizzle);
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void EmitFSwizzleAdd(EmitContext& ctx, IR::Inst& inst, ScalarF32 op_a, ScalarF32 op_b,
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ScalarU32 swizzle);
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void EmitDPdxFine(EmitContext& ctx, IR::Inst& inst, ScalarF32 op_a);
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void EmitDPdxFine(EmitContext& ctx, IR::Inst& inst, ScalarF32 op_a);
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void EmitDPdyFine(EmitContext& ctx, IR::Inst& inst, ScalarF32 op_a);
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void EmitDPdyFine(EmitContext& ctx, IR::Inst& inst, ScalarF32 op_a);
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void EmitDPdxCoarse(EmitContext& ctx, IR::Inst& inst, ScalarF32 op_a);
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void EmitDPdxCoarse(EmitContext& ctx, IR::Inst& inst, ScalarF32 op_a);
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@ -95,8 +95,17 @@ void EmitShuffleButterfly(EmitContext& ctx, IR::Inst& inst, ScalarU32 value, Sca
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Shuffle(ctx, inst, value, index, clamp, segmentation_mask, "XOR");
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Shuffle(ctx, inst, value, index, clamp, segmentation_mask, "XOR");
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}
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}
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void EmitFSwizzleAdd(EmitContext&, ScalarF32, ScalarF32, ScalarU32) {
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void EmitFSwizzleAdd(EmitContext& ctx, IR::Inst& inst, ScalarF32 op_a, ScalarF32 op_b,
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throw NotImplementedException("GLASM instruction");
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ScalarU32 swizzle) {
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const auto ret{ctx.reg_alloc.Define(inst)};
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ctx.Add("AND.U RC.z,{}.threadid,3;"
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"SHL.U RC.z,RC.z,1;"
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"SHR.U RC.z,{},RC.z;"
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"AND.U RC.z,RC.z,3;"
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"MUL.F RC.x,{},FSWZA[RC.z];"
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"MUL.F RC.y,{},FSWZB[RC.z];"
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"ADD.F {}.x,RC.x,RC.y;",
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ctx.stage_name, swizzle, op_a, op_b, ret);
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}
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}
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void EmitDPdxFine(EmitContext& ctx, IR::Inst& inst, ScalarF32 p) {
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void EmitDPdxFine(EmitContext& ctx, IR::Inst& inst, ScalarF32 p) {
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