shader: Implement VOTE
This commit is contained in:
parent
d40faa1db0
commit
3d07cef009
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@ -15,6 +15,7 @@ add_library(shader_recompiler STATIC
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backend/spirv/emit_spirv_memory.cpp
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backend/spirv/emit_spirv_select.cpp
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backend/spirv/emit_spirv_undefined.cpp
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backend/spirv/emit_spirv_vote.cpp
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environment.h
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exception.h
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file_environment.cpp
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@ -122,6 +123,7 @@ add_library(shader_recompiler STATIC
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frontend/maxwell/translate/impl/select_source_with_predicate.cpp
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frontend/maxwell/translate/impl/texture_fetch.cpp
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frontend/maxwell/translate/impl/texture_fetch_swizzled.cpp
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frontend/maxwell/translate/impl/vote.cpp
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frontend/maxwell/translate/translate.cpp
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frontend/maxwell/translate/translate.h
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ir_opt/collect_shader_info_pass.cpp
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@ -259,6 +259,10 @@ void EmitContext::DefineInputs(const Info& info, Stage stage) {
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if (info.uses_local_invocation_id) {
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local_invocation_id = DefineInput(*this, U32[3], spv::BuiltIn::LocalInvocationId);
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}
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if (profile.warp_size_potentially_larger_than_guest && info.uses_subgroup_vote) {
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subgroup_local_invocation_id =
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DefineInput(*this, U32[1], spv::BuiltIn::SubgroupLocalInvocationId);
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}
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if (info.loads_position) {
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const bool is_fragment{stage != Stage::Fragment};
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const spv::BuiltIn built_in{is_fragment ? spv::BuiltIn::Position : spv::BuiltIn::FragCoord};
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@ -82,6 +82,7 @@ public:
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Id workgroup_id{};
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Id local_invocation_id{};
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Id subgroup_local_invocation_id{};
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Id instance_id{};
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Id instance_index{};
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Id base_instance{};
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@ -96,7 +97,7 @@ public:
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std::array<Id, 32> output_generics{};
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std::array<Id, 8> frag_color{};
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Id frag_depth {};
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Id frag_depth{};
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std::vector<Id> interfaces;
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@ -224,6 +224,15 @@ void SetupCapabilities(const Profile& profile, const Info& info, EmitContext& ct
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ctx.AddExtension("SPV_KHR_shader_draw_parameters");
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ctx.AddCapability(spv::Capability::DrawParameters);
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}
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if (info.uses_subgroup_vote && profile.support_vote) {
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ctx.AddExtension("SPV_KHR_shader_ballot");
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ctx.AddCapability(spv::Capability::SubgroupBallotKHR);
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if (!profile.warp_size_potentially_larger_than_guest) {
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// vote ops are only used when not taking the long path
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ctx.AddExtension("SPV_KHR_subgroup_vote");
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ctx.AddCapability(spv::Capability::SubgroupVoteKHR);
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}
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}
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// TODO: Track this usage
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ctx.AddCapability(spv::Capability::ImageGatherExtended);
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}
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@ -346,5 +346,9 @@ Id EmitImageSampleDrefImplicitLod(EmitContext& ctx, IR::Inst* inst, const IR::Va
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Id coords, Id dref, Id bias_lc, Id offset);
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Id EmitImageSampleDrefExplicitLod(EmitContext& ctx, IR::Inst* inst, const IR::Value& index,
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Id coords, Id dref, Id lod_lc, Id offset);
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Id EmitVoteAll(EmitContext& ctx, Id pred);
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Id EmitVoteAny(EmitContext& ctx, Id pred);
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Id EmitVoteEqual(EmitContext& ctx, Id pred);
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Id EmitSubgroupBallot(EmitContext& ctx, Id pred);
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} // namespace Shader::Backend::SPIRV
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@ -0,0 +1,58 @@
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// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "shader_recompiler/backend/spirv/emit_spirv.h"
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namespace Shader::Backend::SPIRV {
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namespace {
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Id LargeWarpBallot(EmitContext& ctx, Id ballot) {
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const Id shift{ctx.Constant(ctx.U32[1], 5)};
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const Id local_index{ctx.OpLoad(ctx.U32[1], ctx.subgroup_local_invocation_id)};
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return ctx.OpVectorExtractDynamic(ctx.U32[1], ballot, local_index);
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}
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} // Anonymous namespace
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Id EmitVoteAll(EmitContext& ctx, Id pred) {
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if (!ctx.profile.warp_size_potentially_larger_than_guest) {
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return ctx.OpSubgroupAllKHR(ctx.U1, pred);
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}
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const Id mask_ballot{ctx.OpSubgroupBallotKHR(ctx.U32[4], ctx.true_value)};
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const Id active_mask{LargeWarpBallot(ctx, mask_ballot)};
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const Id ballot{LargeWarpBallot(ctx, ctx.OpSubgroupBallotKHR(ctx.U32[4], pred))};
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const Id lhs{ctx.OpBitwiseAnd(ctx.U32[1], ballot, active_mask)};
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return ctx.OpIEqual(ctx.U1, lhs, active_mask);
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}
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Id EmitVoteAny(EmitContext& ctx, Id pred) {
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if (!ctx.profile.warp_size_potentially_larger_than_guest) {
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return ctx.OpSubgroupAnyKHR(ctx.U1, pred);
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}
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const Id mask_ballot{ctx.OpSubgroupBallotKHR(ctx.U32[4], ctx.true_value)};
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const Id active_mask{LargeWarpBallot(ctx, mask_ballot)};
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const Id ballot{LargeWarpBallot(ctx, ctx.OpSubgroupBallotKHR(ctx.U32[4], pred))};
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const Id lhs{ctx.OpBitwiseAnd(ctx.U32[1], ballot, active_mask)};
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return ctx.OpINotEqual(ctx.U1, lhs, ctx.u32_zero_value);
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}
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Id EmitVoteEqual(EmitContext& ctx, Id pred) {
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if (!ctx.profile.warp_size_potentially_larger_than_guest) {
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return ctx.OpSubgroupAllEqualKHR(ctx.U1, pred);
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}
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const Id mask_ballot{ctx.OpSubgroupBallotKHR(ctx.U32[4], ctx.true_value)};
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const Id active_mask{LargeWarpBallot(ctx, mask_ballot)};
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const Id ballot{LargeWarpBallot(ctx, ctx.OpSubgroupBallotKHR(ctx.U32[4], pred))};
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const Id lhs{ctx.OpBitwiseXor(ctx.U32[1], ballot, active_mask)};
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return ctx.OpLogicalOr(ctx.U1, ctx.OpIEqual(ctx.U1, lhs, ctx.u32_zero_value),
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ctx.OpIEqual(ctx.U1, lhs, active_mask));
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}
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Id EmitSubgroupBallot(EmitContext& ctx, Id pred) {
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const Id ballot{ctx.OpSubgroupBallotKHR(ctx.U32[4], pred)};
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if (!ctx.profile.warp_size_potentially_larger_than_guest) {
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return ctx.OpCompositeExtract(ctx.U32[1], ballot, 0U);
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}
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return LargeWarpBallot(ctx, ballot);
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}
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} // namespace Shader::Backend::SPIRV
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@ -1444,4 +1444,20 @@ F32 IREmitter::ImageSampleDrefExplicitLod(const Value& handle, const Value& coor
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return Inst<F32>(op, Flags{info}, handle, coords, dref, lod_lc, offset);
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}
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U1 IREmitter::VoteAll(const U1& value) {
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return Inst<U1>(Opcode::VoteAll, value);
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}
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U1 IREmitter::VoteAny(const U1& value) {
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return Inst<U1>(Opcode::VoteAny, value);
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}
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U1 IREmitter::VoteEqual(const U1& value) {
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return Inst<U1>(Opcode::VoteEqual, value);
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}
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U32 IREmitter::SubgroupBallot(const U1& value) {
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return Inst<U32>(Opcode::SubgroupBallot, value);
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}
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} // namespace Shader::IR
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@ -234,6 +234,11 @@ public:
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const Value& offset, const F32& lod_clamp,
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TextureInstInfo info);
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[[nodiscard]] U1 VoteAll(const U1& value);
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[[nodiscard]] U1 VoteAny(const U1& value);
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[[nodiscard]] U1 VoteEqual(const U1& value);
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[[nodiscard]] U32 SubgroupBallot(const U1& value);
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private:
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IR::Block::iterator insertion_point;
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@ -355,3 +355,9 @@ OPCODE(ImageSampleImplicitLod, F32x4, U32,
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OPCODE(ImageSampleExplicitLod, F32x4, U32, Opaque, Opaque, Opaque, )
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OPCODE(ImageSampleDrefImplicitLod, F32, U32, Opaque, F32, Opaque, Opaque, )
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OPCODE(ImageSampleDrefExplicitLod, F32, U32, Opaque, F32, Opaque, Opaque, )
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// Vote operations
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OPCODE(VoteAll, U1, U1, )
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OPCODE(VoteAny, U1, U1, )
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OPCODE(VoteEqual, U1, U1, )
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OPCODE(SubgroupBallot, U32, U1, )
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@ -417,10 +417,6 @@ void TranslatorVisitor::VMNMX(u64) {
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ThrowNotImplemented(Opcode::VMNMX);
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}
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void TranslatorVisitor::VOTE(u64) {
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ThrowNotImplemented(Opcode::VOTE);
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}
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void TranslatorVisitor::VOTE_vtg(u64) {
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ThrowNotImplemented(Opcode::VOTE_vtg);
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}
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@ -0,0 +1,52 @@
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// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <optional>
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#include "common/bit_field.h"
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#include "common/common_types.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
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namespace Shader::Maxwell {
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namespace {
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enum class VoteOp : u64 {
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ALL,
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ANY,
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EQ,
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};
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[[nodiscard]] IR::U1 VoteOperation(IR::IREmitter& ir, const IR::U1& pred, VoteOp vote_op) {
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switch (vote_op) {
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case VoteOp::ALL:
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return ir.VoteAll(pred);
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case VoteOp::ANY:
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return ir.VoteAny(pred);
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case VoteOp::EQ:
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return ir.VoteEqual(pred);
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default:
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throw NotImplementedException("Invalid VOTE op {}", vote_op);
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}
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}
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void Vote(TranslatorVisitor& v, u64 insn) {
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union {
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u64 insn;
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BitField<0, 8, IR::Reg> dest_reg;
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BitField<39, 3, IR::Pred> pred_a;
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BitField<42, 1, u64> neg_pred_a;
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BitField<45, 3, IR::Pred> pred_b;
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BitField<48, 2, VoteOp> vote_op;
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} const vote{insn};
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const IR::U1 vote_pred{v.ir.GetPred(vote.pred_a, vote.neg_pred_a != 0)};
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v.ir.SetPred(vote.pred_b, VoteOperation(v.ir, vote_pred, vote.vote_op));
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v.X(vote.dest_reg, v.ir.SubgroupBallot(vote_pred));
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}
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} // Anonymous namespace
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void TranslatorVisitor::VOTE(u64 insn) {
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Vote(*this, insn);
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}
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} // namespace Shader::Maxwell
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@ -359,6 +359,12 @@ void VisitUsages(Info& info, IR::Inst& inst) {
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inst.GetAssociatedPseudoOperation(IR::Opcode::GetSparseFromOp) != nullptr;
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break;
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}
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case IR::Opcode::VoteAll:
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case IR::Opcode::VoteAny:
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case IR::Opcode::VoteEqual:
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case IR::Opcode::SubgroupBallot:
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info.uses_subgroup_vote = true;
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break;
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default:
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break;
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}
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@ -19,6 +19,8 @@ struct Profile {
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bool support_fp16_signed_zero_nan_preserve{};
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bool support_fp32_signed_zero_nan_preserve{};
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bool support_fp64_signed_zero_nan_preserve{};
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bool support_vote{};
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bool warp_size_potentially_larger_than_guest{};
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// FClamp is broken and OpFMax + OpFMin should be used instead
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bool has_broken_spirv_clamp{};
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@ -80,6 +80,7 @@ struct Info {
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bool uses_sampled_1d{};
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bool uses_sparse_residency{};
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bool uses_demote_to_helper_invocation{};
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bool uses_subgroup_vote{};
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IR::Type used_constant_buffer_types{};
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@ -36,13 +36,18 @@ ComputePipeline::ComputePipeline(const Device& device, VKDescriptorPool& descrip
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descriptor_update_template = std::move(tuple.descriptor_update_template);
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descriptor_allocator = DescriptorAllocator(descriptor_pool, *descriptor_set_layout);
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const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT subgroup_size_ci{
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.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_REQUIRED_SUBGROUP_SIZE_CREATE_INFO_EXT,
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.pNext = nullptr,
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.requiredSubgroupSize = GuestWarpSize,
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};
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pipeline = device.GetLogical().CreateComputePipeline({
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.sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,
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.pNext = nullptr,
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.flags = 0,
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.stage{
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.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
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.pNext = nullptr,
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.pNext = device.IsExtSubgroupSizeControlSupported() ? &subgroup_size_ci : nullptr,
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.flags = 0,
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.stage = VK_SHADER_STAGE_COMPUTE_BIT,
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.module = *spv_module,
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@ -455,6 +455,8 @@ PipelineCache::PipelineCache(RasterizerVulkan& rasterizer_, Tegra::GPU& gpu_,
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float_control.shaderSignedZeroInfNanPreserveFloat32 != VK_FALSE,
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.support_fp64_signed_zero_nan_preserve =
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float_control.shaderSignedZeroInfNanPreserveFloat64 != VK_FALSE,
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.support_vote = true,
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.warp_size_potentially_larger_than_guest = device.IsWarpSizePotentiallyBiggerThanGuest(),
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.has_broken_spirv_clamp = driver_id == VK_DRIVER_ID_INTEL_PROPRIETARY_WINDOWS_KHR,
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};
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}
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@ -737,6 +737,7 @@ std::vector<const char*> Device::LoadExtensions(bool requires_surface) {
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subgroup_properties.maxSubgroupSize >= GuestWarpSize) {
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extensions.push_back(VK_EXT_SUBGROUP_SIZE_CONTROL_EXTENSION_NAME);
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guest_warp_stages = subgroup_properties.requiredSubgroupSizeStages;
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ext_subgroup_size_control = true;
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}
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} else {
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is_warp_potentially_bigger = true;
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@ -193,6 +193,11 @@ public:
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return ext_shader_viewport_index_layer;
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}
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/// Returns true if the device supports VK_EXT_subgroup_size_control.
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bool IsExtSubgroupSizeControlSupported() const {
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return ext_subgroup_size_control;
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}
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/// Returns true if the device supports VK_EXT_transform_feedback.
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bool IsExtTransformFeedbackSupported() const {
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return ext_transform_feedback;
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bool ext_depth_range_unrestricted{}; ///< Support for VK_EXT_depth_range_unrestricted.
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bool ext_shader_viewport_index_layer{}; ///< Support for VK_EXT_shader_viewport_index_layer.
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bool ext_tooling_info{}; ///< Support for VK_EXT_tooling_info.
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bool ext_subgroup_size_control{}; ///< Support for VK_EXT_subgroup_size_control.
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bool ext_transform_feedback{}; ///< Support for VK_EXT_transform_feedback.
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bool ext_custom_border_color{}; ///< Support for VK_EXT_custom_border_color.
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bool ext_extended_dynamic_state{}; ///< Support for VK_EXT_extended_dynamic_state.
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