logging: Rename category "Core_ARM11" to "Core_ARM".
This commit is contained in:
parent
3f0caefdf5
commit
45db4bb3ea
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@ -21,7 +21,7 @@ namespace Log {
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SUB(Common, Filesystem) \
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SUB(Common, Memory) \
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CLS(Core) \
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SUB(Core, ARM11) \
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SUB(Core, ARM) \
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SUB(Core, Timing) \
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CLS(Config) \
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CLS(Debug) \
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@ -37,7 +37,7 @@ enum class Class : ClassType {
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Common_Filesystem, ///< Filesystem interface library
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Common_Memory, ///< Memory mapping and management functions
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Core, ///< LLE emulation core
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Core_ARM11, ///< ARM11 CPU core
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Core_ARM, ///< ARM CPU core
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Core_Timing, ///< CoreTiming functions
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Config, ///< Emulator configuration (including commandline)
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Debug, ///< Debugging tools
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@ -230,7 +230,7 @@ static unsigned int DPO(RotateRightByRegister)(ARMul_State* cpu, unsigned int sh
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}
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#define DEBUG_MSG \
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LOG_DEBUG(Core_ARM11, "inst is %x", inst); \
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LOG_DEBUG(Core_ARM, "inst is %x", inst); \
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CITRA_IGNORE_EXIT(0)
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#define LnSWoUB(s) glue(LnSWoUB, s)
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@ -769,7 +769,7 @@ static ThumbDecodeStatus DecodeThumbInstruction(u32 inst, u32 addr, u32* arm_ins
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inst_index = table_length - 4;
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*ptr_inst_base = arm_instruction_trans[inst_index](tinstr, inst_index);
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} else {
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LOG_ERROR(Core_ARM11, "thumb decoder error");
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LOG_ERROR(Core_ARM, "thumb decoder error");
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}
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break;
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case 28:
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@ -827,9 +827,9 @@ static unsigned int InterpreterTranslateInstruction(const ARMul_State* cpu, cons
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int idx;
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if (DecodeARMInstruction(inst, &idx) == ARMDecodeStatus::FAILURE) {
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LOG_ERROR(Core_ARM11, "Decode failure.\tPC: [0x%08" PRIX32 "]\tInstruction: %08" PRIX32,
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LOG_ERROR(Core_ARM, "Decode failure.\tPC: [0x%08" PRIX32 "]\tInstruction: %08" PRIX32,
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phys_addr, inst);
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LOG_ERROR(Core_ARM11, "cpsr=0x%" PRIX32 ", cpu->TFlag=%d, r15=0x%08" PRIX32, cpu->Cpsr,
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LOG_ERROR(Core_ARM, "cpsr=0x%" PRIX32 ", cpu->TFlag=%d, r15=0x%08" PRIX32, cpu->Cpsr,
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cpu->TFlag, cpu->Reg[15]);
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CITRA_IGNORE_EXIT(-1);
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}
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@ -1802,7 +1802,7 @@ BIC_INST : {
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BKPT_INST : {
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if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
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bkpt_inst* const inst_cream = (bkpt_inst*)inst_base->component;
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LOG_DEBUG(Core_ARM11, "Breakpoint instruction hit. Immediate: 0x%08X", inst_cream->imm);
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LOG_DEBUG(Core_ARM, "Breakpoint instruction hit. Immediate: 0x%08X", inst_cream->imm);
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}
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cpu->Reg[15] += cpu->GetInstructionSize();
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INC_PC(sizeof(bkpt_inst));
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@ -2017,7 +2017,7 @@ EOR_INST : {
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}
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LDC_INST : {
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// Instruction not implemented
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// LOG_CRITICAL(Core_ARM11, "unimplemented instruction");
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// LOG_CRITICAL(Core_ARM, "unimplemented instruction");
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cpu->Reg[15] += cpu->GetInstructionSize();
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INC_PC(sizeof(ldc_inst));
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FETCH_INST;
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@ -2368,7 +2368,7 @@ MCRR_INST : {
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if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
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mcrr_inst* const inst_cream = (mcrr_inst*)inst_base->component;
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LOG_ERROR(Core_ARM11, "MCRR executed | Coprocessor: %u, CRm %u, opc1: %u, Rt: %u, Rt2: %u",
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LOG_ERROR(Core_ARM, "MCRR executed | Coprocessor: %u, CRm %u, opc1: %u, Rt: %u, Rt2: %u",
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inst_cream->cp_num, inst_cream->crm, inst_cream->opcode_1, inst_cream->rt,
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inst_cream->rt2);
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}
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@ -2451,7 +2451,7 @@ MRRC_INST : {
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if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
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mcrr_inst* const inst_cream = (mcrr_inst*)inst_base->component;
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LOG_ERROR(Core_ARM11, "MRRC executed | Coprocessor: %u, CRm %u, opc1: %u, Rt: %u, Rt2: %u",
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LOG_ERROR(Core_ARM, "MRRC executed | Coprocessor: %u, CRm %u, opc1: %u, Rt: %u, Rt2: %u",
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inst_cream->cp_num, inst_cream->crm, inst_cream->opcode_1, inst_cream->rt,
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inst_cream->rt2);
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}
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@ -3078,7 +3078,7 @@ SETEND_INST : {
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else
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cpu->Cpsr &= ~(1 << 9);
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LOG_WARNING(Core_ARM11, "SETEND %s executed", big_endian ? "BE" : "LE");
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LOG_WARNING(Core_ARM, "SETEND %s executed", big_endian ? "BE" : "LE");
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cpu->Reg[15] += cpu->GetInstructionSize();
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INC_PC(sizeof(setend_inst));
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@ -3089,7 +3089,7 @@ SETEND_INST : {
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SEV_INST : {
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// Stubbed, as SEV is a hint instruction.
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if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
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LOG_TRACE(Core_ARM11, "SEV executed.");
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LOG_TRACE(Core_ARM, "SEV executed.");
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}
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cpu->Reg[15] += cpu->GetInstructionSize();
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@ -3539,7 +3539,7 @@ SSAT16_INST : {
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STC_INST : {
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// Instruction not implemented
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// LOG_CRITICAL(Core_ARM11, "unimplemented instruction");
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// LOG_CRITICAL(Core_ARM, "unimplemented instruction");
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cpu->Reg[15] += cpu->GetInstructionSize();
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INC_PC(sizeof(stc_inst));
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FETCH_INST;
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@ -4529,7 +4529,7 @@ UXTB16_INST : {
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WFE_INST : {
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// Stubbed, as WFE is a hint instruction.
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if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
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LOG_TRACE(Core_ARM11, "WFE executed.");
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LOG_TRACE(Core_ARM, "WFE executed.");
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}
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cpu->Reg[15] += cpu->GetInstructionSize();
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@ -4541,7 +4541,7 @@ WFE_INST : {
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WFI_INST : {
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// Stubbed, as WFI is a hint instruction.
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if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
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LOG_TRACE(Core_ARM11, "WFI executed.");
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LOG_TRACE(Core_ARM, "WFI executed.");
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}
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cpu->Reg[15] += cpu->GetInstructionSize();
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@ -4553,7 +4553,7 @@ WFI_INST : {
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YIELD_INST : {
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// Stubbed, as YIELD is a hint instruction.
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if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
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LOG_TRACE(Core_ARM11, "YIELD executed.");
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LOG_TRACE(Core_ARM, "YIELD executed.");
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}
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cpu->Reg[15] += cpu->GetInstructionSize();
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@ -185,7 +185,7 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(cdp)(unsigned int inst, int index) {
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inst_cream->opcode_1 = BITS(inst, 20, 23);
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inst_cream->inst = inst;
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LOG_TRACE(Core_ARM11, "inst %x index %x", inst, index);
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LOG_TRACE(Core_ARM, "inst %x index %x", inst, index);
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return inst_base;
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}
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static ARM_INST_PTR INTERPRETER_TRANSLATE(clrex)(unsigned int inst, int index) {
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@ -428,7 +428,7 @@ u32 ARMul_State::ReadCP15Register(u32 crn, u32 opcode_1, u32 crm, u32 opcode_2)
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}
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}
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LOG_ERROR(Core_ARM11, "MRC CRn=%u, CRm=%u, OP1=%u OP2=%u is not implemented. Returning zero.",
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LOG_ERROR(Core_ARM, "MRC CRn=%u, CRm=%u, OP1=%u OP2=%u is not implemented. Returning zero.",
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crn, crm, opcode_1, opcode_2);
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return 0;
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}
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@ -90,23 +90,23 @@ void VMOVR(ARMul_State* state, u32 single, u32 d, u32 m) {
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/* Miscellaneous functions */
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s32 vfp_get_float(ARMul_State* state, unsigned int reg) {
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LOG_TRACE(Core_ARM11, "VFP get float: s%d=[%08x]", reg, state->ExtReg[reg]);
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LOG_TRACE(Core_ARM, "VFP get float: s%d=[%08x]", reg, state->ExtReg[reg]);
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return state->ExtReg[reg];
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}
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void vfp_put_float(ARMul_State* state, s32 val, unsigned int reg) {
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LOG_TRACE(Core_ARM11, "VFP put float: s%d <= [%08x]", reg, val);
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LOG_TRACE(Core_ARM, "VFP put float: s%d <= [%08x]", reg, val);
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state->ExtReg[reg] = val;
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}
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u64 vfp_get_double(ARMul_State* state, unsigned int reg) {
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u64 result = ((u64)state->ExtReg[reg * 2 + 1]) << 32 | state->ExtReg[reg * 2];
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LOG_TRACE(Core_ARM11, "VFP get double: s[%d-%d]=[%016llx]", reg * 2 + 1, reg * 2, result);
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LOG_TRACE(Core_ARM, "VFP get double: s[%d-%d]=[%016llx]", reg * 2 + 1, reg * 2, result);
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return result;
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}
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void vfp_put_double(ARMul_State* state, u64 val, unsigned int reg) {
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LOG_TRACE(Core_ARM11, "VFP put double: s[%d-%d] <= [%08x-%08x]", reg * 2 + 1, reg * 2,
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LOG_TRACE(Core_ARM, "VFP put double: s[%d-%d] <= [%08x-%08x]", reg * 2 + 1, reg * 2,
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(u32)(val >> 32), (u32)(val & 0xffffffff));
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state->ExtReg[reg * 2] = (u32)(val & 0xffffffff);
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state->ExtReg[reg * 2 + 1] = (u32)(val >> 32);
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@ -116,10 +116,10 @@ void vfp_put_double(ARMul_State* state, u64 val, unsigned int reg) {
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* Process bitmask of exception conditions. (from vfpmodule.c)
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*/
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void vfp_raise_exceptions(ARMul_State* state, u32 exceptions, u32 inst, u32 fpscr) {
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LOG_TRACE(Core_ARM11, "VFP: raising exceptions %08x", exceptions);
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LOG_TRACE(Core_ARM, "VFP: raising exceptions %08x", exceptions);
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if (exceptions == VFP_EXCEPTION_ERROR) {
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LOG_CRITICAL(Core_ARM11, "unhandled bounce %x", inst);
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LOG_CRITICAL(Core_ARM, "unhandled bounce %x", inst);
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Crash();
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}
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@ -22,7 +22,7 @@
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#include "core/arm/skyeye_common/vfp/vfp_helper.h" /* for references to cdp SoftFloat functions */
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#define VFP_DEBUG_UNTESTED(x) LOG_TRACE(Core_ARM11, "in func %s, " #x " untested", __FUNCTION__);
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#define VFP_DEBUG_UNTESTED(x) LOG_TRACE(Core_ARM, "in func %s, " #x " untested", __FUNCTION__);
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#define CHECK_VFP_ENABLED
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#define CHECK_VFP_CDP_RET vfp_raise_exceptions(cpu, ret, inst_cream->instr, cpu->VFP[VFP_FPSCR]);
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@ -62,7 +62,7 @@ static struct vfp_double vfp_double_default_qnan = {
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};
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static void vfp_double_dump(const char* str, struct vfp_double* d) {
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LOG_TRACE(Core_ARM11, "VFP: %s: sign=%d exponent=%d significand=%016llx", str, d->sign != 0,
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LOG_TRACE(Core_ARM, "VFP: %s: sign=%d exponent=%d significand=%016llx", str, d->sign != 0,
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d->exponent, d->significand);
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}
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@ -164,7 +164,7 @@ u32 vfp_double_normaliseround(ARMul_State* state, int dd, struct vfp_double* vd,
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} else if ((rmode == FPSCR_ROUND_PLUSINF) ^ (vd->sign != 0))
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incr = (1ULL << (VFP_DOUBLE_LOW_BITS + 1)) - 1;
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LOG_TRACE(Core_ARM11, "VFP: rounding increment = 0x%08llx", incr);
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LOG_TRACE(Core_ARM, "VFP: rounding increment = 0x%08llx", incr);
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/*
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* Is our rounding going to overflow?
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@ -219,7 +219,7 @@ pack:
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vfp_double_dump("pack: final", vd);
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{
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s64 d = vfp_double_pack(vd);
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LOG_TRACE(Core_ARM11, "VFP: %s: d(d%d)=%016llx exceptions=%08x", func, dd, d, exceptions);
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LOG_TRACE(Core_ARM, "VFP: %s: d(d%d)=%016llx exceptions=%08x", func, dd, d, exceptions);
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vfp_put_double(state, d, dd);
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}
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return exceptions;
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@ -272,25 +272,25 @@ static u32 vfp_propagate_nan(struct vfp_double* vdd, struct vfp_double* vdn, str
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* Extended operations
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*/
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static u32 vfp_double_fabs(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) {
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LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__);
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LOG_TRACE(Core_ARM, "In %s", __FUNCTION__);
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vfp_put_double(state, vfp_double_packed_abs(vfp_get_double(state, dm)), dd);
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return 0;
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}
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static u32 vfp_double_fcpy(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) {
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LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__);
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LOG_TRACE(Core_ARM, "In %s", __FUNCTION__);
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vfp_put_double(state, vfp_get_double(state, dm), dd);
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return 0;
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}
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static u32 vfp_double_fneg(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) {
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LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__);
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LOG_TRACE(Core_ARM, "In %s", __FUNCTION__);
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vfp_put_double(state, vfp_double_packed_negate(vfp_get_double(state, dm)), dd);
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return 0;
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}
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static u32 vfp_double_fsqrt(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) {
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LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__);
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LOG_TRACE(Core_ARM, "In %s", __FUNCTION__);
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vfp_double vdm, vdd, *vdp;
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int ret, tm;
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u32 exceptions = 0;
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@ -387,7 +387,7 @@ static u32 vfp_compare(ARMul_State* state, int dd, int signal_on_qnan, int dm, u
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s64 d, m;
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u32 ret = 0;
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LOG_TRACE(Core_ARM11, "In %s, state=0x%p, fpscr=0x%x", __FUNCTION__, state, fpscr);
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LOG_TRACE(Core_ARM, "In %s, state=0x%p, fpscr=0x%x", __FUNCTION__, state, fpscr);
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m = vfp_get_double(state, dm);
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if (vfp_double_packed_exponent(m) == 2047 && vfp_double_packed_mantissa(m)) {
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ret |= FPSCR_CFLAG | FPSCR_VFLAG;
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@ -444,28 +444,28 @@ static u32 vfp_compare(ARMul_State* state, int dd, int signal_on_qnan, int dm, u
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ret |= FPSCR_CFLAG;
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}
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}
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LOG_TRACE(Core_ARM11, "In %s, state=0x%p, ret=0x%x", __FUNCTION__, state, ret);
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LOG_TRACE(Core_ARM, "In %s, state=0x%p, ret=0x%x", __FUNCTION__, state, ret);
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return ret;
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}
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static u32 vfp_double_fcmp(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) {
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LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__);
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LOG_TRACE(Core_ARM, "In %s", __FUNCTION__);
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return vfp_compare(state, dd, 0, dm, fpscr);
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}
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static u32 vfp_double_fcmpe(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) {
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LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__);
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LOG_TRACE(Core_ARM, "In %s", __FUNCTION__);
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return vfp_compare(state, dd, 1, dm, fpscr);
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}
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static u32 vfp_double_fcmpz(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) {
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LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__);
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LOG_TRACE(Core_ARM, "In %s", __FUNCTION__);
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return vfp_compare(state, dd, 0, VFP_REG_ZERO, fpscr);
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}
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static u32 vfp_double_fcmpez(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) {
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LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__);
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LOG_TRACE(Core_ARM, "In %s", __FUNCTION__);
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return vfp_compare(state, dd, 1, VFP_REG_ZERO, fpscr);
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}
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@ -475,7 +475,7 @@ static u32 vfp_double_fcvts(ARMul_State* state, int sd, int unused, int dm, u32
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int tm;
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u32 exceptions = 0;
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LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__);
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LOG_TRACE(Core_ARM, "In %s", __FUNCTION__);
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exceptions |= vfp_double_unpack(&vdm, vfp_get_double(state, dm), fpscr);
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tm = vfp_double_type(&vdm);
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@ -516,7 +516,7 @@ static u32 vfp_double_fuito(ARMul_State* state, int dd, int unused, int dm, u32
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struct vfp_double vdm;
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u32 m = vfp_get_float(state, dm);
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LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__);
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LOG_TRACE(Core_ARM, "In %s", __FUNCTION__);
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vdm.sign = 0;
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vdm.exponent = 1023 + 63 - 1;
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vdm.significand = (u64)m;
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@ -528,7 +528,7 @@ static u32 vfp_double_fsito(ARMul_State* state, int dd, int unused, int dm, u32
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struct vfp_double vdm;
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u32 m = vfp_get_float(state, dm);
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LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__);
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LOG_TRACE(Core_ARM, "In %s", __FUNCTION__);
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vdm.sign = (m & 0x80000000) >> 16;
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vdm.exponent = 1023 + 63 - 1;
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vdm.significand = vdm.sign ? (~m + 1) : m;
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@ -542,7 +542,7 @@ static u32 vfp_double_ftoui(ARMul_State* state, int sd, int unused, int dm, u32
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int rmode = fpscr & FPSCR_RMODE_MASK;
|
||||
int tm;
|
||||
|
||||
LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__);
|
||||
LOG_TRACE(Core_ARM, "In %s", __FUNCTION__);
|
||||
exceptions |= vfp_double_unpack(&vdm, vfp_get_double(state, dm), fpscr);
|
||||
|
||||
/*
|
||||
|
@ -611,7 +611,7 @@ static u32 vfp_double_ftoui(ARMul_State* state, int sd, int unused, int dm, u32
|
|||
}
|
||||
}
|
||||
|
||||
LOG_TRACE(Core_ARM11, "VFP: ftoui: d(s%d)=%08x exceptions=%08x", sd, d, exceptions);
|
||||
LOG_TRACE(Core_ARM, "VFP: ftoui: d(s%d)=%08x exceptions=%08x", sd, d, exceptions);
|
||||
|
||||
vfp_put_float(state, d, sd);
|
||||
|
||||
|
@ -619,7 +619,7 @@ static u32 vfp_double_ftoui(ARMul_State* state, int sd, int unused, int dm, u32
|
|||
}
|
||||
|
||||
static u32 vfp_double_ftouiz(ARMul_State* state, int sd, int unused, int dm, u32 fpscr) {
|
||||
LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__);
|
||||
LOG_TRACE(Core_ARM, "In %s", __FUNCTION__);
|
||||
return vfp_double_ftoui(state, sd, unused, dm,
|
||||
(fpscr & ~FPSCR_RMODE_MASK) | FPSCR_ROUND_TOZERO);
|
||||
}
|
||||
|
@ -630,7 +630,7 @@ static u32 vfp_double_ftosi(ARMul_State* state, int sd, int unused, int dm, u32
|
|||
int rmode = fpscr & FPSCR_RMODE_MASK;
|
||||
int tm;
|
||||
|
||||
LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__);
|
||||
LOG_TRACE(Core_ARM, "In %s", __FUNCTION__);
|
||||
exceptions |= vfp_double_unpack(&vdm, vfp_get_double(state, dm), fpscr);
|
||||
vfp_double_dump("VDM", &vdm);
|
||||
|
||||
|
@ -694,7 +694,7 @@ static u32 vfp_double_ftosi(ARMul_State* state, int sd, int unused, int dm, u32
|
|||
}
|
||||
}
|
||||
|
||||
LOG_TRACE(Core_ARM11, "VFP: ftosi: d(s%d)=%08x exceptions=%08x", sd, d, exceptions);
|
||||
LOG_TRACE(Core_ARM, "VFP: ftosi: d(s%d)=%08x exceptions=%08x", sd, d, exceptions);
|
||||
|
||||
vfp_put_float(state, (s32)d, sd);
|
||||
|
||||
|
@ -702,7 +702,7 @@ static u32 vfp_double_ftosi(ARMul_State* state, int sd, int unused, int dm, u32
|
|||
}
|
||||
|
||||
static u32 vfp_double_ftosiz(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) {
|
||||
LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__);
|
||||
LOG_TRACE(Core_ARM, "In %s", __FUNCTION__);
|
||||
return vfp_double_ftosi(state, dd, unused, dm,
|
||||
(fpscr & ~FPSCR_RMODE_MASK) | FPSCR_ROUND_TOZERO);
|
||||
}
|
||||
|
@ -784,7 +784,7 @@ u32 vfp_double_add(struct vfp_double* vdd, struct vfp_double* vdn, struct vfp_do
|
|||
u64 m_sig;
|
||||
|
||||
if (vdn->significand & (1ULL << 63) || vdm->significand & (1ULL << 63)) {
|
||||
LOG_INFO(Core_ARM11, "VFP: bad FP values in %s", __func__);
|
||||
LOG_INFO(Core_ARM, "VFP: bad FP values in %s", __func__);
|
||||
vfp_double_dump("VDN", vdn);
|
||||
vfp_double_dump("VDM", vdm);
|
||||
}
|
||||
|
@ -849,7 +849,7 @@ u32 vfp_double_multiply(struct vfp_double* vdd, struct vfp_double* vdn, struct v
|
|||
*/
|
||||
if (vdn->exponent < vdm->exponent) {
|
||||
std::swap(vdm, vdn);
|
||||
LOG_TRACE(Core_ARM11, "VFP: swapping M <-> N");
|
||||
LOG_TRACE(Core_ARM, "VFP: swapping M <-> N");
|
||||
}
|
||||
|
||||
vdd->sign = vdn->sign ^ vdm->sign;
|
||||
|
@ -931,7 +931,7 @@ static u32 vfp_double_multiply_accumulate(ARMul_State* state, int dd, int dn, in
|
|||
* sd = sd + (sn * sm)
|
||||
*/
|
||||
static u32 vfp_double_fmac(ARMul_State* state, int dd, int dn, int dm, u32 fpscr) {
|
||||
LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__);
|
||||
LOG_TRACE(Core_ARM, "In %s", __FUNCTION__);
|
||||
return vfp_double_multiply_accumulate(state, dd, dn, dm, fpscr, 0, "fmac");
|
||||
}
|
||||
|
||||
|
@ -939,7 +939,7 @@ static u32 vfp_double_fmac(ARMul_State* state, int dd, int dn, int dm, u32 fpscr
|
|||
* sd = sd - (sn * sm)
|
||||
*/
|
||||
static u32 vfp_double_fnmac(ARMul_State* state, int dd, int dn, int dm, u32 fpscr) {
|
||||
LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__);
|
||||
LOG_TRACE(Core_ARM, "In %s", __FUNCTION__);
|
||||
return vfp_double_multiply_accumulate(state, dd, dn, dm, fpscr, NEG_MULTIPLY, "fnmac");
|
||||
}
|
||||
|
||||
|
@ -947,7 +947,7 @@ static u32 vfp_double_fnmac(ARMul_State* state, int dd, int dn, int dm, u32 fpsc
|
|||
* sd = -sd + (sn * sm)
|
||||
*/
|
||||
static u32 vfp_double_fmsc(ARMul_State* state, int dd, int dn, int dm, u32 fpscr) {
|
||||
LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__);
|
||||
LOG_TRACE(Core_ARM, "In %s", __FUNCTION__);
|
||||
return vfp_double_multiply_accumulate(state, dd, dn, dm, fpscr, NEG_SUBTRACT, "fmsc");
|
||||
}
|
||||
|
||||
|
@ -955,7 +955,7 @@ static u32 vfp_double_fmsc(ARMul_State* state, int dd, int dn, int dm, u32 fpscr
|
|||
* sd = -sd - (sn * sm)
|
||||
*/
|
||||
static u32 vfp_double_fnmsc(ARMul_State* state, int dd, int dn, int dm, u32 fpscr) {
|
||||
LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__);
|
||||
LOG_TRACE(Core_ARM, "In %s", __FUNCTION__);
|
||||
return vfp_double_multiply_accumulate(state, dd, dn, dm, fpscr, NEG_SUBTRACT | NEG_MULTIPLY,
|
||||
"fnmsc");
|
||||
}
|
||||
|
@ -967,7 +967,7 @@ static u32 vfp_double_fmul(ARMul_State* state, int dd, int dn, int dm, u32 fpscr
|
|||
struct vfp_double vdd, vdn, vdm;
|
||||
u32 exceptions = 0;
|
||||
|
||||
LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__);
|
||||
LOG_TRACE(Core_ARM, "In %s", __FUNCTION__);
|
||||
exceptions |= vfp_double_unpack(&vdn, vfp_get_double(state, dn), fpscr);
|
||||
if (vdn.exponent == 0 && vdn.significand)
|
||||
vfp_double_normalise_denormal(&vdn);
|
||||
|
@ -987,7 +987,7 @@ static u32 vfp_double_fnmul(ARMul_State* state, int dd, int dn, int dm, u32 fpsc
|
|||
struct vfp_double vdd, vdn, vdm;
|
||||
u32 exceptions = 0;
|
||||
|
||||
LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__);
|
||||
LOG_TRACE(Core_ARM, "In %s", __FUNCTION__);
|
||||
exceptions |= vfp_double_unpack(&vdn, vfp_get_double(state, dn), fpscr);
|
||||
if (vdn.exponent == 0 && vdn.significand)
|
||||
vfp_double_normalise_denormal(&vdn);
|
||||
|
@ -1009,7 +1009,7 @@ static u32 vfp_double_fadd(ARMul_State* state, int dd, int dn, int dm, u32 fpscr
|
|||
struct vfp_double vdd, vdn, vdm;
|
||||
u32 exceptions = 0;
|
||||
|
||||
LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__);
|
||||
LOG_TRACE(Core_ARM, "In %s", __FUNCTION__);
|
||||
exceptions |= vfp_double_unpack(&vdn, vfp_get_double(state, dn), fpscr);
|
||||
if (vdn.exponent == 0 && vdn.significand)
|
||||
vfp_double_normalise_denormal(&vdn);
|
||||
|
@ -1030,7 +1030,7 @@ static u32 vfp_double_fsub(ARMul_State* state, int dd, int dn, int dm, u32 fpscr
|
|||
struct vfp_double vdd, vdn, vdm;
|
||||
u32 exceptions = 0;
|
||||
|
||||
LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__);
|
||||
LOG_TRACE(Core_ARM, "In %s", __FUNCTION__);
|
||||
exceptions |= vfp_double_unpack(&vdn, vfp_get_double(state, dn), fpscr);
|
||||
if (vdn.exponent == 0 && vdn.significand)
|
||||
vfp_double_normalise_denormal(&vdn);
|
||||
|
@ -1057,7 +1057,7 @@ static u32 vfp_double_fdiv(ARMul_State* state, int dd, int dn, int dm, u32 fpscr
|
|||
u32 exceptions = 0;
|
||||
int tm, tn;
|
||||
|
||||
LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__);
|
||||
LOG_TRACE(Core_ARM, "In %s", __FUNCTION__);
|
||||
exceptions |= vfp_double_unpack(&vdn, vfp_get_double(state, dn), fpscr);
|
||||
exceptions |= vfp_double_unpack(&vdm, vfp_get_double(state, dm), fpscr);
|
||||
|
||||
|
@ -1175,7 +1175,7 @@ u32 vfp_double_cpdo(ARMul_State* state, u32 inst, u32 fpscr) {
|
|||
unsigned int vecitr, veclen, vecstride;
|
||||
struct op* fop;
|
||||
|
||||
LOG_TRACE(Core_ARM11, "In %s", __FUNCTION__);
|
||||
LOG_TRACE(Core_ARM, "In %s", __FUNCTION__);
|
||||
vecstride = (1 + ((fpscr & FPSCR_STRIDE_MASK) == FPSCR_STRIDE_MASK));
|
||||
|
||||
fop = (op == FOP_EXT) ? &fops_ext[FEXT_TO_IDX(inst)] : &fops[FOP_TO_IDX(op)];
|
||||
|
@ -1206,7 +1206,7 @@ u32 vfp_double_cpdo(ARMul_State* state, u32 inst, u32 fpscr) {
|
|||
else
|
||||
veclen = fpscr & FPSCR_LENGTH_MASK;
|
||||
|
||||
LOG_TRACE(Core_ARM11, "VFP: vecstride=%u veclen=%u", vecstride,
|
||||
LOG_TRACE(Core_ARM, "VFP: vecstride=%u veclen=%u", vecstride,
|
||||
(veclen >> FPSCR_LENGTH_BIT) + 1);
|
||||
|
||||
if (!fop->fn) {
|
||||
|
@ -1220,14 +1220,14 @@ u32 vfp_double_cpdo(ARMul_State* state, u32 inst, u32 fpscr) {
|
|||
|
||||
type = (fop->flags & OP_SD) ? 's' : 'd';
|
||||
if (op == FOP_EXT)
|
||||
LOG_TRACE(Core_ARM11, "VFP: itr%d (%c%u) = op[%u] (d%u)", vecitr >> FPSCR_LENGTH_BIT,
|
||||
LOG_TRACE(Core_ARM, "VFP: itr%d (%c%u) = op[%u] (d%u)", vecitr >> FPSCR_LENGTH_BIT,
|
||||
type, dest, dn, dm);
|
||||
else
|
||||
LOG_TRACE(Core_ARM11, "VFP: itr%d (%c%u) = (d%u) op[%u] (d%u)",
|
||||
LOG_TRACE(Core_ARM, "VFP: itr%d (%c%u) = (d%u) op[%u] (d%u)",
|
||||
vecitr >> FPSCR_LENGTH_BIT, type, dest, dn, FOP_TO_IDX(op), dm);
|
||||
|
||||
except = fop->fn(state, dest, dn, dm, fpscr);
|
||||
LOG_TRACE(Core_ARM11, "VFP: itr%d: exceptions=%08x", vecitr >> FPSCR_LENGTH_BIT, except);
|
||||
LOG_TRACE(Core_ARM, "VFP: itr%d: exceptions=%08x", vecitr >> FPSCR_LENGTH_BIT, except);
|
||||
|
||||
exceptions |= except & ~VFP_NAN_FLAG;
|
||||
|
||||
|
|
|
@ -65,7 +65,7 @@ static struct vfp_single vfp_single_default_qnan = {
|
|||
};
|
||||
|
||||
static void vfp_single_dump(const char* str, struct vfp_single* s) {
|
||||
LOG_TRACE(Core_ARM11, "%s: sign=%d exponent=%d significand=%08x", str, s->sign != 0,
|
||||
LOG_TRACE(Core_ARM, "%s: sign=%d exponent=%d significand=%08x", str, s->sign != 0,
|
||||
s->exponent, s->significand);
|
||||
}
|
||||
|
||||
|
@ -167,7 +167,7 @@ u32 vfp_single_normaliseround(ARMul_State* state, int sd, struct vfp_single* vs,
|
|||
} else if ((rmode == FPSCR_ROUND_PLUSINF) ^ (vs->sign != 0))
|
||||
incr = (1 << (VFP_SINGLE_LOW_BITS + 1)) - 1;
|
||||
|
||||
LOG_TRACE(Core_ARM11, "rounding increment = 0x%08x", incr);
|
||||
LOG_TRACE(Core_ARM, "rounding increment = 0x%08x", incr);
|
||||
|
||||
/*
|
||||
* Is our rounding going to overflow?
|
||||
|
@ -222,7 +222,7 @@ pack:
|
|||
vfp_single_dump("pack: final", vs);
|
||||
{
|
||||
s32 d = vfp_single_pack(vs);
|
||||
LOG_TRACE(Core_ARM11, "%s: d(s%d)=%08x exceptions=%08x", func, sd, d, exceptions);
|
||||
LOG_TRACE(Core_ARM, "%s: d(s%d)=%08x exceptions=%08x", func, sd, d, exceptions);
|
||||
vfp_put_float(state, d, sd);
|
||||
}
|
||||
|
||||
|
@ -305,7 +305,7 @@ u32 vfp_estimate_sqrt_significand(u32 exponent, u32 significand) {
|
|||
u32 z, a;
|
||||
|
||||
if ((significand & 0xc0000000) != 0x40000000) {
|
||||
LOG_TRACE(Core_ARM11, "invalid significand");
|
||||
LOG_TRACE(Core_ARM, "invalid significand");
|
||||
}
|
||||
|
||||
a = significand << 1;
|
||||
|
@ -395,7 +395,7 @@ static u32 vfp_single_fsqrt(ARMul_State* state, int sd, int unused, s32 m, u32 f
|
|||
term = (u64)vsd.significand * vsd.significand;
|
||||
rem = ((u64)vsm.significand << 32) - term;
|
||||
|
||||
LOG_TRACE(Core_ARM11, "term=%016" PRIx64 "rem=%016" PRIx64, term, rem);
|
||||
LOG_TRACE(Core_ARM, "term=%016" PRIx64 "rem=%016" PRIx64, term, rem);
|
||||
|
||||
while (rem < 0) {
|
||||
vsd.significand -= 1;
|
||||
|
@ -634,7 +634,7 @@ static u32 vfp_single_ftoui(ARMul_State* state, int sd, int unused, s32 m, u32 f
|
|||
}
|
||||
}
|
||||
|
||||
LOG_TRACE(Core_ARM11, "ftoui: d(s%d)=%08x exceptions=%08x", sd, d, exceptions);
|
||||
LOG_TRACE(Core_ARM, "ftoui: d(s%d)=%08x exceptions=%08x", sd, d, exceptions);
|
||||
|
||||
vfp_put_float(state, d, sd);
|
||||
|
||||
|
@ -715,7 +715,7 @@ static u32 vfp_single_ftosi(ARMul_State* state, int sd, int unused, s32 m, u32 f
|
|||
}
|
||||
}
|
||||
|
||||
LOG_TRACE(Core_ARM11, "ftosi: d(s%d)=%08x exceptions=%08x", sd, d, exceptions);
|
||||
LOG_TRACE(Core_ARM, "ftosi: d(s%d)=%08x exceptions=%08x", sd, d, exceptions);
|
||||
|
||||
vfp_put_float(state, (s32)d, sd);
|
||||
|
||||
|
@ -802,7 +802,7 @@ static u32 vfp_single_add(struct vfp_single* vsd, struct vfp_single* vsn, struct
|
|||
u32 exp_diff, m_sig;
|
||||
|
||||
if (vsn->significand & 0x80000000 || vsm->significand & 0x80000000) {
|
||||
LOG_WARNING(Core_ARM11, "bad FP values");
|
||||
LOG_WARNING(Core_ARM, "bad FP values");
|
||||
vfp_single_dump("VSN", vsn);
|
||||
vfp_single_dump("VSM", vsm);
|
||||
}
|
||||
|
@ -867,7 +867,7 @@ static u32 vfp_single_multiply(struct vfp_single* vsd, struct vfp_single* vsn,
|
|||
*/
|
||||
if (vsn->exponent < vsm->exponent) {
|
||||
std::swap(vsm, vsn);
|
||||
LOG_TRACE(Core_ARM11, "swapping M <-> N");
|
||||
LOG_TRACE(Core_ARM, "swapping M <-> N");
|
||||
}
|
||||
|
||||
vsd->sign = vsn->sign ^ vsm->sign;
|
||||
|
@ -919,7 +919,7 @@ static u32 vfp_single_multiply_accumulate(ARMul_State* state, int sd, int sn, s3
|
|||
s32 v;
|
||||
|
||||
v = vfp_get_float(state, sn);
|
||||
LOG_TRACE(Core_ARM11, "s%u = %08x", sn, v);
|
||||
LOG_TRACE(Core_ARM, "s%u = %08x", sn, v);
|
||||
exceptions |= vfp_single_unpack(&vsn, v, fpscr);
|
||||
if (vsn.exponent == 0 && vsn.significand)
|
||||
vfp_single_normalise_denormal(&vsn);
|
||||
|
@ -934,7 +934,7 @@ static u32 vfp_single_multiply_accumulate(ARMul_State* state, int sd, int sn, s3
|
|||
vsp.sign = vfp_sign_negate(vsp.sign);
|
||||
|
||||
v = vfp_get_float(state, sd);
|
||||
LOG_TRACE(Core_ARM11, "s%u = %08x", sd, v);
|
||||
LOG_TRACE(Core_ARM, "s%u = %08x", sd, v);
|
||||
exceptions |= vfp_single_unpack(&vsn, v, fpscr);
|
||||
if (vsn.exponent == 0 && vsn.significand != 0)
|
||||
vfp_single_normalise_denormal(&vsn);
|
||||
|
@ -955,7 +955,7 @@ static u32 vfp_single_multiply_accumulate(ARMul_State* state, int sd, int sn, s3
|
|||
* sd = sd + (sn * sm)
|
||||
*/
|
||||
static u32 vfp_single_fmac(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr) {
|
||||
LOG_TRACE(Core_ARM11, "s%u = %08x", sn, sd);
|
||||
LOG_TRACE(Core_ARM, "s%u = %08x", sn, sd);
|
||||
return vfp_single_multiply_accumulate(state, sd, sn, m, fpscr, 0, "fmac");
|
||||
}
|
||||
|
||||
|
@ -964,7 +964,7 @@ static u32 vfp_single_fmac(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr)
|
|||
*/
|
||||
static u32 vfp_single_fnmac(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr) {
|
||||
// TODO: this one has its arguments inverted, investigate.
|
||||
LOG_TRACE(Core_ARM11, "s%u = %08x", sd, sn);
|
||||
LOG_TRACE(Core_ARM, "s%u = %08x", sd, sn);
|
||||
return vfp_single_multiply_accumulate(state, sd, sn, m, fpscr, NEG_MULTIPLY, "fnmac");
|
||||
}
|
||||
|
||||
|
@ -972,7 +972,7 @@ static u32 vfp_single_fnmac(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr
|
|||
* sd = -sd + (sn * sm)
|
||||
*/
|
||||
static u32 vfp_single_fmsc(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr) {
|
||||
LOG_TRACE(Core_ARM11, "s%u = %08x", sn, sd);
|
||||
LOG_TRACE(Core_ARM, "s%u = %08x", sn, sd);
|
||||
return vfp_single_multiply_accumulate(state, sd, sn, m, fpscr, NEG_SUBTRACT, "fmsc");
|
||||
}
|
||||
|
||||
|
@ -980,7 +980,7 @@ static u32 vfp_single_fmsc(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr)
|
|||
* sd = -sd - (sn * sm)
|
||||
*/
|
||||
static u32 vfp_single_fnmsc(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr) {
|
||||
LOG_TRACE(Core_ARM11, "s%u = %08x", sn, sd);
|
||||
LOG_TRACE(Core_ARM, "s%u = %08x", sn, sd);
|
||||
return vfp_single_multiply_accumulate(state, sd, sn, m, fpscr, NEG_SUBTRACT | NEG_MULTIPLY,
|
||||
"fnmsc");
|
||||
}
|
||||
|
@ -993,7 +993,7 @@ static u32 vfp_single_fmul(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr)
|
|||
u32 exceptions = 0;
|
||||
s32 n = vfp_get_float(state, sn);
|
||||
|
||||
LOG_TRACE(Core_ARM11, "s%u = %08x", sn, n);
|
||||
LOG_TRACE(Core_ARM, "s%u = %08x", sn, n);
|
||||
|
||||
exceptions |= vfp_single_unpack(&vsn, n, fpscr);
|
||||
if (vsn.exponent == 0 && vsn.significand)
|
||||
|
@ -1015,7 +1015,7 @@ static u32 vfp_single_fnmul(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr
|
|||
u32 exceptions = 0;
|
||||
s32 n = vfp_get_float(state, sn);
|
||||
|
||||
LOG_TRACE(Core_ARM11, "s%u = %08x", sn, n);
|
||||
LOG_TRACE(Core_ARM, "s%u = %08x", sn, n);
|
||||
|
||||
exceptions |= vfp_single_unpack(&vsn, n, fpscr);
|
||||
if (vsn.exponent == 0 && vsn.significand)
|
||||
|
@ -1038,7 +1038,7 @@ static u32 vfp_single_fadd(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr)
|
|||
u32 exceptions = 0;
|
||||
s32 n = vfp_get_float(state, sn);
|
||||
|
||||
LOG_TRACE(Core_ARM11, "s%u = %08x", sn, n);
|
||||
LOG_TRACE(Core_ARM, "s%u = %08x", sn, n);
|
||||
|
||||
/*
|
||||
* Unpack and normalise denormals.
|
||||
|
@ -1060,7 +1060,7 @@ static u32 vfp_single_fadd(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr)
|
|||
* sd = sn - sm
|
||||
*/
|
||||
static u32 vfp_single_fsub(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr) {
|
||||
LOG_TRACE(Core_ARM11, "s%u = %08x", sn, sd);
|
||||
LOG_TRACE(Core_ARM, "s%u = %08x", sn, sd);
|
||||
/*
|
||||
* Subtraction is addition with one sign inverted. Unpack the second operand to perform FTZ if
|
||||
* necessary, we can't let fadd do this because a denormal in m might get flushed to +0 in FTZ
|
||||
|
@ -1089,7 +1089,7 @@ static u32 vfp_single_fdiv(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr)
|
|||
s32 n = vfp_get_float(state, sn);
|
||||
int tm, tn;
|
||||
|
||||
LOG_TRACE(Core_ARM11, "s%u = %08x", sn, n);
|
||||
LOG_TRACE(Core_ARM, "s%u = %08x", sn, n);
|
||||
|
||||
exceptions |= vfp_single_unpack(&vsn, n, fpscr);
|
||||
exceptions |= vfp_single_unpack(&vsm, m, fpscr);
|
||||
|
@ -1229,10 +1229,10 @@ u32 vfp_single_cpdo(ARMul_State* state, u32 inst, u32 fpscr) {
|
|||
else
|
||||
veclen = fpscr & FPSCR_LENGTH_MASK;
|
||||
|
||||
LOG_TRACE(Core_ARM11, "vecstride=%u veclen=%u", vecstride, (veclen >> FPSCR_LENGTH_BIT) + 1);
|
||||
LOG_TRACE(Core_ARM, "vecstride=%u veclen=%u", vecstride, (veclen >> FPSCR_LENGTH_BIT) + 1);
|
||||
|
||||
if (!fop->fn) {
|
||||
LOG_CRITICAL(Core_ARM11, "could not find single op %d, inst=0x%x@0x%x", FEXT_TO_IDX(inst),
|
||||
LOG_CRITICAL(Core_ARM, "could not find single op %d, inst=0x%x@0x%x", FEXT_TO_IDX(inst),
|
||||
inst, state->Reg[15]);
|
||||
Crash();
|
||||
goto invalid;
|
||||
|
@ -1245,14 +1245,14 @@ u32 vfp_single_cpdo(ARMul_State* state, u32 inst, u32 fpscr) {
|
|||
|
||||
type = (fop->flags & OP_DD) ? 'd' : 's';
|
||||
if (op == FOP_EXT)
|
||||
LOG_TRACE(Core_ARM11, "itr%d (%c%u) = op[%u] (s%u=%08x)", vecitr >> FPSCR_LENGTH_BIT,
|
||||
LOG_TRACE(Core_ARM, "itr%d (%c%u) = op[%u] (s%u=%08x)", vecitr >> FPSCR_LENGTH_BIT,
|
||||
type, dest, sn, sm, m);
|
||||
else
|
||||
LOG_TRACE(Core_ARM11, "itr%d (%c%u) = (s%u) op[%u] (s%u=%08x)",
|
||||
LOG_TRACE(Core_ARM, "itr%d (%c%u) = (s%u) op[%u] (s%u=%08x)",
|
||||
vecitr >> FPSCR_LENGTH_BIT, type, dest, sn, FOP_TO_IDX(op), sm, m);
|
||||
|
||||
except = fop->fn(state, dest, sn, m, fpscr);
|
||||
LOG_TRACE(Core_ARM11, "itr%d: exceptions=%08x", vecitr >> FPSCR_LENGTH_BIT, except);
|
||||
LOG_TRACE(Core_ARM, "itr%d: exceptions=%08x", vecitr >> FPSCR_LENGTH_BIT, except);
|
||||
|
||||
exceptions |= except & ~VFP_NAN_FLAG;
|
||||
|
||||
|
|
|
@ -52,7 +52,7 @@ System::ResultStatus System::RunLoop(int tight_loop) {
|
|||
// If we don't have a currently active thread then don't execute instructions,
|
||||
// instead advance to the next event and try to yield to the next thread
|
||||
if (Kernel::GetCurrentThread() == nullptr) {
|
||||
LOG_TRACE(Core_ARM11, "Idling");
|
||||
LOG_TRACE(Core_ARM, "Idling");
|
||||
CoreTiming::Idle();
|
||||
CoreTiming::Advance();
|
||||
PrepareReschedule();
|
||||
|
|
Reference in New Issue