dyncom: Implement SHADD8/SHADD16/SHSUB8/SHSUB16/SHASX/SHSAX
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08b6cf778d
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524da47698
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@ -2236,13 +2236,48 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(sel)(unsigned int inst, int index)
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return inst_base;
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return inst_base;
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}
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(setend)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SETEND"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(setend)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SETEND"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(shadd16)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SHADD16"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(shadd8)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SHADD8"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(shadd8)(unsigned int inst, int index)
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ARM_INST_PTR INTERPRETER_TRANSLATE(shaddsubx)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SHADDSUBX"); }
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{
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ARM_INST_PTR INTERPRETER_TRANSLATE(shsub16)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SHSUB16"); }
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arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst));
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ARM_INST_PTR INTERPRETER_TRANSLATE(shsub8)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SHSUB8"); }
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generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component;
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ARM_INST_PTR INTERPRETER_TRANSLATE(shsubaddx)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SHSUBADDX"); }
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inst_base->cond = BITS(inst, 28, 31);
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inst_base->idx = index;
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inst_base->br = NON_BRANCH;
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inst_base->load_r15 = 0;
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inst_cream->op1 = BITS(inst, 20, 21);
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inst_cream->op2 = BITS(inst, 5, 7);
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inst_cream->Rm = BITS(inst, 0, 3);
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inst_cream->Rn = BITS(inst, 16, 19);
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inst_cream->Rd = BITS(inst, 12, 15);
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return inst_base;
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(shadd16)(unsigned int inst, int index)
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{
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return INTERPRETER_TRANSLATE(shadd8)(inst, index);
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(shaddsubx)(unsigned int inst, int index)
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{
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return INTERPRETER_TRANSLATE(shadd8)(inst, index);
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(shsub8)(unsigned int inst, int index)
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{
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return INTERPRETER_TRANSLATE(shadd8)(inst, index);
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(shsub16)(unsigned int inst, int index)
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{
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return INTERPRETER_TRANSLATE(shadd8)(inst, index);
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(shsubaddx)(unsigned int inst, int index)
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{
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return INTERPRETER_TRANSLATE(shadd8)(inst, index);
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(smla)(unsigned int inst, int index)
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ARM_INST_PTR INTERPRETER_TRANSLATE(smla)(unsigned int inst, int index)
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{
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{
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arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(smla_inst));
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arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(smla_inst));
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@ -5176,12 +5211,79 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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}
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}
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SETEND_INST:
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SETEND_INST:
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SHADD16_INST:
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SHADD8_INST:
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SHADD8_INST:
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SHADD16_INST:
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SHADDSUBX_INST:
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SHADDSUBX_INST:
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SHSUB16_INST:
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SHSUB8_INST:
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SHSUB8_INST:
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SHSUB16_INST:
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SHSUBADDX_INST:
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SHSUBADDX_INST:
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{
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component;
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const u8 op2 = inst_cream->op2;
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const u32 rm_val = RM;
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const u32 rn_val = RN;
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if (op2 == 0x00 || op2 == 0x01 || op2 == 0x02 || op2 == 0x03) {
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s32 lo_result = 0;
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s32 hi_result = 0;
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// SHADD16
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if (op2 == 0x00) {
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lo_result = ((s16)(rn_val & 0xFFFF) + (s16)(rm_val & 0xFFFF)) >> 1;
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hi_result = ((s16)((rn_val >> 16) & 0xFFFF) + (s16)((rm_val >> 16) & 0xFFFF)) >> 1;
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}
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// SHASX
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else if (op2 == 0x01) {
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lo_result = ((s16)(rn_val & 0xFFFF) - (s16)((rm_val >> 16) & 0xFFFF)) >> 1;
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hi_result = ((s16)((rn_val >> 16) & 0xFFFF) + (s16)(rm_val & 0xFFFF)) >> 1;
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}
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// SHSAX
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else if (op2 == 0x02) {
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lo_result = ((s16)(rn_val & 0xFFFF) + (s16)((rm_val >> 16) & 0xFFFF)) >> 1;
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hi_result = ((s16)((rn_val >> 16) & 0xFFFF) - (s16)(rm_val & 0xFFFF)) >> 1;
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}
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// SHSUB16
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else if (op2 == 0x03) {
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lo_result = ((s16)(rn_val & 0xFFFF) - (s16)(rm_val & 0xFFFF)) >> 1;
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hi_result = ((s16)((rn_val >> 16) & 0xFFFF) - (s16)((rm_val >> 16) & 0xFFFF)) >> 1;
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}
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RD = ((lo_result & 0xFFFF) | ((hi_result & 0xFFFF) << 16));
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}
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else if (op2 == 0x04 || op2 == 0x07) {
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s16 lo_val1, lo_val2;
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s16 hi_val1, hi_val2;
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// SHADD8
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if (op2 == 0x04) {
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lo_val1 = ((s8)(rn_val & 0xFF) + (s8)(rm_val & 0xFF)) >> 1;
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lo_val2 = ((s8)((rn_val >> 8) & 0xFF) + (s8)((rm_val >> 8) & 0xFF)) >> 1;
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hi_val1 = ((s8)((rn_val >> 16) & 0xFF) + (s8)((rm_val >> 16) & 0xFF)) >> 1;
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hi_val2 = ((s8)((rn_val >> 24) & 0xFF) + (s8)((rm_val >> 24) & 0xFF)) >> 1;
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}
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// SHSUB8
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else {
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lo_val1 = ((s8)(rn_val & 0xFF) - (s8)(rm_val & 0xFF)) >> 1;
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lo_val2 = ((s8)((rn_val >> 8) & 0xFF) - (s8)((rm_val >> 8) & 0xFF)) >> 1;
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hi_val1 = ((s8)((rn_val >> 16) & 0xFF) - (s8)((rm_val >> 16) & 0xFF)) >> 1;
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hi_val2 = ((s8)((rn_val >> 24) & 0xFF) - (s8)((rm_val >> 24) & 0xFF)) >> 1;
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}
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RD = (lo_val1 & 0xFF) | ((lo_val2 & 0xFF) << 8) | ((hi_val1 & 0xFF) << 16) | ((hi_val2 & 0xFF) << 24);
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}
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}
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cpu->Reg[15] += GET_INST_SIZE(cpu);
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INC_PC(sizeof(generic_arm_inst));
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FETCH_INST;
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GOTO_NEXT_INST;
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}
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SMLA_INST:
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SMLA_INST:
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{
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{
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if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
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if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
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