Merge pull request #1458 from FernandoS27/fix-render-target-block-settings
Fixed block height settings for RenderTargets and Depth Buffers
This commit is contained in:
commit
6d82c4adf9
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@ -36,9 +36,9 @@ public:
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RenderTargetFormat format;
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RenderTargetFormat format;
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BitField<0, 1, u32> linear;
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BitField<0, 1, u32> linear;
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union {
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union {
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BitField<0, 4, u32> block_depth;
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BitField<0, 4, u32> block_width;
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BitField<4, 4, u32> block_height;
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BitField<4, 4, u32> block_height;
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BitField<8, 4, u32> block_width;
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BitField<8, 4, u32> block_depth;
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};
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};
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u32 depth;
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u32 depth;
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u32 layer;
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u32 layer;
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@ -53,10 +53,20 @@ public:
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address_low);
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address_low);
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}
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}
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u32 BlockWidth() const {
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// The block width is stored in log2 format.
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return 1 << block_width;
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}
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u32 BlockHeight() const {
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u32 BlockHeight() const {
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// The block height is stored in log2 format.
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// The block height is stored in log2 format.
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return 1 << block_height;
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return 1 << block_height;
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}
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}
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u32 BlockDepth() const {
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// The block depth is stored in log2 format.
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return 1 << block_depth;
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}
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};
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};
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static_assert(sizeof(Surface) == 0x28, "Surface has incorrect size");
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static_assert(sizeof(Surface) == 0x28, "Surface has incorrect size");
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@ -347,6 +347,16 @@ public:
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DecrWrap = 8,
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DecrWrap = 8,
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};
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};
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enum class MemoryLayout : u32 {
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Linear = 0,
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BlockLinear = 1,
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};
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enum class InvMemoryLayout : u32 {
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BlockLinear = 0,
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Linear = 1,
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};
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struct Cull {
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struct Cull {
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enum class FrontFace : u32 {
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enum class FrontFace : u32 {
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ClockWise = 0x0900,
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ClockWise = 0x0900,
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@ -432,7 +442,12 @@ public:
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u32 width;
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u32 width;
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u32 height;
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u32 height;
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Tegra::RenderTargetFormat format;
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Tegra::RenderTargetFormat format;
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u32 block_dimensions;
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union {
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BitField<0, 3, u32> block_width;
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BitField<4, 3, u32> block_height;
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BitField<8, 3, u32> block_depth;
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BitField<12, 1, InvMemoryLayout> type;
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} memory_layout;
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u32 array_mode;
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u32 array_mode;
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u32 layer_stride;
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u32 layer_stride;
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u32 base_layer;
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u32 base_layer;
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@ -562,7 +577,12 @@ public:
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u32 address_high;
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u32 address_high;
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u32 address_low;
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u32 address_low;
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Tegra::DepthFormat format;
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Tegra::DepthFormat format;
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u32 block_dimensions;
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union {
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BitField<0, 4, u32> block_width;
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BitField<4, 4, u32> block_height;
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BitField<8, 4, u32> block_depth;
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BitField<20, 1, InvMemoryLayout> type;
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} memory_layout;
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u32 layer_stride;
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u32 layer_stride;
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GPUVAddr Address() const {
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GPUVAddr Address() const {
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@ -45,7 +45,9 @@ static VAddr TryGetCpuAddr(Tegra::GPUVAddr gpu_addr) {
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SurfaceParams params{};
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SurfaceParams params{};
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params.addr = TryGetCpuAddr(config.tic.Address());
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params.addr = TryGetCpuAddr(config.tic.Address());
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params.is_tiled = config.tic.IsTiled();
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params.is_tiled = config.tic.IsTiled();
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params.block_width = params.is_tiled ? config.tic.BlockWidth() : 0,
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params.block_height = params.is_tiled ? config.tic.BlockHeight() : 0,
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params.block_height = params.is_tiled ? config.tic.BlockHeight() : 0,
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params.block_depth = params.is_tiled ? config.tic.BlockDepth() : 0,
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params.pixel_format =
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params.pixel_format =
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PixelFormatFromTextureFormat(config.tic.format, config.tic.r_type.Value());
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PixelFormatFromTextureFormat(config.tic.format, config.tic.r_type.Value());
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params.component_type = ComponentTypeFromTexture(config.tic.r_type.Value());
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params.component_type = ComponentTypeFromTexture(config.tic.r_type.Value());
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@ -97,8 +99,11 @@ static VAddr TryGetCpuAddr(Tegra::GPUVAddr gpu_addr) {
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const auto& config{Core::System::GetInstance().GPU().Maxwell3D().regs.rt[index]};
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const auto& config{Core::System::GetInstance().GPU().Maxwell3D().regs.rt[index]};
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SurfaceParams params{};
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SurfaceParams params{};
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params.addr = TryGetCpuAddr(config.Address());
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params.addr = TryGetCpuAddr(config.Address());
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params.is_tiled = true;
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params.is_tiled =
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params.block_height = Tegra::Texture::TICEntry::DefaultBlockHeight;
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config.memory_layout.type == Tegra::Engines::Maxwell3D::Regs::InvMemoryLayout::BlockLinear;
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params.block_width = 1 << config.memory_layout.block_width;
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params.block_height = 1 << config.memory_layout.block_height;
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params.block_depth = 1 << config.memory_layout.block_depth;
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params.pixel_format = PixelFormatFromRenderTargetFormat(config.format);
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params.pixel_format = PixelFormatFromRenderTargetFormat(config.format);
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params.component_type = ComponentTypeFromRenderTarget(config.format);
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params.component_type = ComponentTypeFromRenderTarget(config.format);
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params.type = GetFormatType(params.pixel_format);
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params.type = GetFormatType(params.pixel_format);
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@ -120,13 +125,16 @@ static VAddr TryGetCpuAddr(Tegra::GPUVAddr gpu_addr) {
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return params;
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return params;
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}
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}
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/*static*/ SurfaceParams SurfaceParams::CreateForDepthBuffer(u32 zeta_width, u32 zeta_height,
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/*static*/ SurfaceParams SurfaceParams::CreateForDepthBuffer(
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Tegra::GPUVAddr zeta_address,
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u32 zeta_width, u32 zeta_height, Tegra::GPUVAddr zeta_address, Tegra::DepthFormat format,
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Tegra::DepthFormat format) {
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u32 block_width, u32 block_height, u32 block_depth,
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Tegra::Engines::Maxwell3D::Regs::InvMemoryLayout type) {
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SurfaceParams params{};
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SurfaceParams params{};
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params.addr = TryGetCpuAddr(zeta_address);
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params.addr = TryGetCpuAddr(zeta_address);
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params.is_tiled = true;
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params.is_tiled = type == Tegra::Engines::Maxwell3D::Regs::InvMemoryLayout::BlockLinear;
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params.block_height = Tegra::Texture::TICEntry::DefaultBlockHeight;
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params.block_width = 1 << std::min(block_width, 5U);
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params.block_height = 1 << std::min(block_height, 5U);
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params.block_depth = 1 << std::min(block_depth, 5U);
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params.pixel_format = PixelFormatFromDepthFormat(format);
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params.pixel_format = PixelFormatFromDepthFormat(format);
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params.component_type = ComponentTypeFromDepthFormat(format);
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params.component_type = ComponentTypeFromDepthFormat(format);
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params.type = GetFormatType(params.pixel_format);
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params.type = GetFormatType(params.pixel_format);
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@ -148,7 +156,9 @@ static VAddr TryGetCpuAddr(Tegra::GPUVAddr gpu_addr) {
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SurfaceParams params{};
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SurfaceParams params{};
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params.addr = TryGetCpuAddr(config.Address());
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params.addr = TryGetCpuAddr(config.Address());
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params.is_tiled = !config.linear;
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params.is_tiled = !config.linear;
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params.block_height = params.is_tiled ? config.BlockHeight() : 0,
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params.block_width = params.is_tiled ? std::min(config.BlockWidth(), 32U) : 0,
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params.block_height = params.is_tiled ? std::min(config.BlockHeight(), 32U) : 0,
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params.block_depth = params.is_tiled ? std::min(config.BlockDepth(), 32U) : 0,
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params.pixel_format = PixelFormatFromRenderTargetFormat(config.format);
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params.pixel_format = PixelFormatFromRenderTargetFormat(config.format);
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params.component_type = ComponentTypeFromRenderTarget(config.format);
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params.component_type = ComponentTypeFromRenderTarget(config.format);
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params.type = GetFormatType(params.pixel_format);
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params.type = GetFormatType(params.pixel_format);
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@ -818,6 +828,11 @@ void CachedSurface::LoadGLBuffer() {
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if (params.is_tiled) {
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if (params.is_tiled) {
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gl_buffer.resize(total_size);
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gl_buffer.resize(total_size);
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ASSERT_MSG(params.block_width == 1, "Block width is defined as {} on texture type {}",
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params.block_width, static_cast<u32>(params.target));
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ASSERT_MSG(params.block_depth == 1, "Block depth is defined as {} on texture type {}",
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params.block_depth, static_cast<u32>(params.target));
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// TODO(bunnei): This only unswizzles and copies a 2D texture - we do not yet know how to do
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// TODO(bunnei): This only unswizzles and copies a 2D texture - we do not yet know how to do
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// this for 3D textures, etc.
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// this for 3D textures, etc.
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switch (params.target) {
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switch (params.target) {
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@ -989,7 +1004,9 @@ Surface RasterizerCacheOpenGL::GetDepthBufferSurface(bool preserve_contents) {
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}
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}
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SurfaceParams depth_params{SurfaceParams::CreateForDepthBuffer(
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SurfaceParams depth_params{SurfaceParams::CreateForDepthBuffer(
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regs.zeta_width, regs.zeta_height, regs.zeta.Address(), regs.zeta.format)};
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regs.zeta_width, regs.zeta_height, regs.zeta.Address(), regs.zeta.format,
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regs.zeta.memory_layout.block_width, regs.zeta.memory_layout.block_height,
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regs.zeta.memory_layout.block_depth, regs.zeta.memory_layout.type)};
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return GetSurface(depth_params, preserve_contents);
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return GetSurface(depth_params, preserve_contents);
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}
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}
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@ -716,9 +716,10 @@ struct SurfaceParams {
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static SurfaceParams CreateForFramebuffer(std::size_t index);
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static SurfaceParams CreateForFramebuffer(std::size_t index);
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/// Creates SurfaceParams for a depth buffer configuration
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/// Creates SurfaceParams for a depth buffer configuration
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static SurfaceParams CreateForDepthBuffer(u32 zeta_width, u32 zeta_height,
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static SurfaceParams CreateForDepthBuffer(
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Tegra::GPUVAddr zeta_address,
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u32 zeta_width, u32 zeta_height, Tegra::GPUVAddr zeta_address, Tegra::DepthFormat format,
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Tegra::DepthFormat format);
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u32 block_width, u32 block_height, u32 block_depth,
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Tegra::Engines::Maxwell3D::Regs::InvMemoryLayout type);
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/// Creates SurfaceParams for a Fermi2D surface copy
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/// Creates SurfaceParams for a Fermi2D surface copy
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static SurfaceParams CreateForFermiCopySurface(
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static SurfaceParams CreateForFermiCopySurface(
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@ -733,7 +734,9 @@ struct SurfaceParams {
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VAddr addr;
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VAddr addr;
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bool is_tiled;
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bool is_tiled;
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u32 block_width;
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u32 block_height;
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u32 block_height;
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u32 block_depth;
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PixelFormat pixel_format;
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PixelFormat pixel_format;
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ComponentType component_type;
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ComponentType component_type;
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SurfaceType type;
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SurfaceType type;
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@ -161,7 +161,9 @@ struct TICEntry {
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BitField<21, 3, TICHeaderVersion> header_version;
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BitField<21, 3, TICHeaderVersion> header_version;
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};
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};
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union {
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union {
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BitField<0, 3, u32> block_width;
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BitField<3, 3, u32> block_height;
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BitField<3, 3, u32> block_height;
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BitField<6, 3, u32> block_depth;
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// High 16 bits of the pitch value
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// High 16 bits of the pitch value
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BitField<0, 16, u32> pitch_high;
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BitField<0, 16, u32> pitch_high;
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@ -202,13 +204,24 @@ struct TICEntry {
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return depth_minus_1 + 1;
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return depth_minus_1 + 1;
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}
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}
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u32 BlockWidth() const {
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ASSERT(IsTiled());
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// The block height is stored in log2 format.
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return 1 << block_width;
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}
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u32 BlockHeight() const {
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u32 BlockHeight() const {
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ASSERT(header_version == TICHeaderVersion::BlockLinear ||
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ASSERT(IsTiled());
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header_version == TICHeaderVersion::BlockLinearColorKey);
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// The block height is stored in log2 format.
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// The block height is stored in log2 format.
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return 1 << block_height;
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return 1 << block_height;
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}
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}
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u32 BlockDepth() const {
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ASSERT(IsTiled());
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// The block height is stored in log2 format.
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return 1 << block_depth;
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}
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bool IsTiled() const {
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bool IsTiled() const {
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return header_version == TICHeaderVersion::BlockLinear ||
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return header_version == TICHeaderVersion::BlockLinear ||
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header_version == TICHeaderVersion::BlockLinearColorKey;
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header_version == TICHeaderVersion::BlockLinearColorKey;
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