Merge pull request #1244 from FernandoS27/ipa
shader_decompiler: Implemented IPA Properly (Stage 1)
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commit
6f09c5b128
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@ -76,6 +76,7 @@ union Attribute {
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Position = 7,
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Attribute_0 = 8,
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Attribute_31 = 39,
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PointCoord = 46,
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// This attribute contains a tuple of (~, ~, InstanceId, VertexId) when inside a vertex
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// shader, and a tuple of (TessCoord.x, TessCoord.y, TessCoord.z, ~) when inside a Tess Eval
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// shader.
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@ -246,6 +247,17 @@ enum class TextureType : u64 {
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enum class IpaInterpMode : u64 { Linear = 0, Perspective = 1, Flat = 2, Sc = 3 };
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enum class IpaSampleMode : u64 { Default = 0, Centroid = 1, Offset = 2 };
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struct IpaMode {
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IpaInterpMode interpolation_mode;
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IpaSampleMode sampling_mode;
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inline bool operator==(const IpaMode& a) {
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return (a.interpolation_mode == interpolation_mode) && (a.sampling_mode == sampling_mode);
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}
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inline bool operator!=(const IpaMode& a) {
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return !((*this) == a);
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}
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};
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union Instruction {
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Instruction& operator=(const Instruction& instr) {
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value = instr.value;
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@ -247,6 +247,7 @@ public:
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const Maxwell3D::Regs::ShaderStage& stage, const std::string& suffix)
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: shader{shader}, declarations{declarations}, stage{stage}, suffix{suffix} {
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BuildRegisterList();
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BuildInputList();
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}
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/**
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@ -343,9 +344,10 @@ public:
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* @param elem The element to use for the operation.
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* @param attribute The input attribute to use as the source value.
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*/
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void SetRegisterToInputAttibute(const Register& reg, u64 elem, Attribute::Index attribute) {
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void SetRegisterToInputAttibute(const Register& reg, u64 elem, Attribute::Index attribute,
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const Tegra::Shader::IpaMode& input_mode) {
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std::string dest = GetRegisterAsFloat(reg);
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std::string src = GetInputAttribute(attribute) + GetSwizzle(elem);
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std::string src = GetInputAttribute(attribute, input_mode) + GetSwizzle(elem);
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shader.AddLine(dest + " = " + src + ';');
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}
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@ -412,12 +414,13 @@ public:
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}
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declarations.AddNewLine();
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for (const auto& index : declr_input_attribute) {
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for (const auto element : declr_input_attribute) {
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// TODO(bunnei): Use proper number of elements for these
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declarations.AddLine("layout(location = " +
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std::to_string(static_cast<u32>(index) -
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static_cast<u32>(Attribute::Index::Attribute_0)) +
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") in vec4 " + GetInputAttribute(index) + ';');
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u32 idx =
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static_cast<u32>(element.first) - static_cast<u32>(Attribute::Index::Attribute_0);
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declarations.AddLine("layout(location = " + std::to_string(idx) + ")" +
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GetInputFlags(element.first) + "in vec4 " +
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GetInputAttribute(element.first, element.second) + ';');
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}
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declarations.AddNewLine();
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@ -532,11 +535,24 @@ private:
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}
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}
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void BuildInputList() {
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const u32 size = static_cast<u32>(Attribute::Index::Attribute_31) -
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static_cast<u32>(Attribute::Index::Attribute_0) + 1;
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declr_input_attribute.reserve(size);
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}
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/// Generates code representing an input attribute register.
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std::string GetInputAttribute(Attribute::Index attribute) {
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std::string GetInputAttribute(Attribute::Index attribute,
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const Tegra::Shader::IpaMode& input_mode) {
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switch (attribute) {
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case Attribute::Index::Position:
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if (stage != Maxwell3D::Regs::ShaderStage::Fragment) {
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return "position";
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} else {
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return "vec4(gl_FragCoord.x, gl_FragCoord.y, gl_FragCoord.z, 1.0)";
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}
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case Attribute::Index::PointCoord:
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return "vec4(gl_PointCoord.x, gl_PointCoord.y, 0, 0)";
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case Attribute::Index::TessCoordInstanceIDVertexID:
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// TODO(Subv): Find out what the values are for the first two elements when inside a
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// vertex shader, and what's the value of the fourth element when inside a Tess Eval
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@ -552,7 +568,14 @@ private:
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static_cast<u32>(Attribute::Index::Attribute_0)};
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if (attribute >= Attribute::Index::Attribute_0 &&
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attribute <= Attribute::Index::Attribute_31) {
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declr_input_attribute.insert(attribute);
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if (declr_input_attribute.count(attribute) == 0) {
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declr_input_attribute[attribute] = input_mode;
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} else {
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if (declr_input_attribute[attribute] != input_mode) {
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LOG_CRITICAL(HW_GPU, "Same Input multiple input modes");
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UNREACHABLE();
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}
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}
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return "input_attribute_" + std::to_string(index);
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}
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@ -563,6 +586,49 @@ private:
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return "vec4(0, 0, 0, 0)";
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}
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std::string GetInputFlags(const Attribute::Index attribute) {
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const Tegra::Shader::IpaSampleMode sample_mode =
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declr_input_attribute[attribute].sampling_mode;
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const Tegra::Shader::IpaInterpMode interp_mode =
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declr_input_attribute[attribute].interpolation_mode;
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std::string out;
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switch (interp_mode) {
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case Tegra::Shader::IpaInterpMode::Flat: {
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out += "flat ";
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break;
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}
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case Tegra::Shader::IpaInterpMode::Linear: {
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out += "noperspective ";
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break;
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}
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case Tegra::Shader::IpaInterpMode::Perspective: {
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// Default, Smooth
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break;
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}
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default: {
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LOG_CRITICAL(HW_GPU, "Unhandled Ipa InterpMode: {}", static_cast<u32>(interp_mode));
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UNREACHABLE();
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}
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}
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switch (sample_mode) {
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case Tegra::Shader::IpaSampleMode::Centroid: {
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// Note not implemented, it can be implemented with the "centroid " keyword in glsl;
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LOG_CRITICAL(HW_GPU, "Ipa Sampler Mode: centroid, not implemented");
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UNREACHABLE();
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break;
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}
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case Tegra::Shader::IpaSampleMode::Default: {
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// Default, n/a
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break;
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}
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default: {
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LOG_CRITICAL(HW_GPU, "Unhandled Ipa SampleMode: {}", static_cast<u32>(sample_mode));
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UNREACHABLE();
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}
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}
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return out;
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}
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/// Generates code representing an output attribute register.
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std::string GetOutputAttribute(Attribute::Index attribute) {
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switch (attribute) {
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@ -593,7 +659,7 @@ private:
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ShaderWriter& shader;
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ShaderWriter& declarations;
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std::vector<GLSLRegister> regs;
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std::set<Attribute::Index> declr_input_attribute;
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std::unordered_map<Attribute::Index, Tegra::Shader::IpaMode> declr_input_attribute;
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std::set<Attribute::Index> declr_output_attribute;
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std::array<ConstBufferEntry, Maxwell3D::Regs::MaxConstBuffers> declr_const_buffers;
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std::vector<SamplerEntry> used_samplers;
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@ -1634,8 +1700,12 @@ private:
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switch (opcode->GetId()) {
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case OpCode::Id::LD_A: {
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ASSERT_MSG(instr.attribute.fmt20.size == 0, "untested");
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// Note: Shouldn't this be interp mode flat? As in no interpolation made.
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Tegra::Shader::IpaMode input_mode{Tegra::Shader::IpaInterpMode::Perspective,
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Tegra::Shader::IpaSampleMode::Default};
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regs.SetRegisterToInputAttibute(instr.gpr0, instr.attribute.fmt20.element,
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instr.attribute.fmt20.index);
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instr.attribute.fmt20.index, input_mode);
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break;
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}
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case OpCode::Id::LD_C: {
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@ -2127,42 +2197,11 @@ private:
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case OpCode::Id::IPA: {
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const auto& attribute = instr.attribute.fmt28;
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const auto& reg = instr.gpr0;
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ASSERT_MSG(instr.ipa.sample_mode == Tegra::Shader::IpaSampleMode::Default,
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"Unhandled IPA sample mode: {}",
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static_cast<u32>(instr.ipa.sample_mode.Value()));
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ASSERT_MSG(instr.ipa.saturate == 0, "IPA saturate not implemented");
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switch (instr.ipa.interp_mode) {
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case Tegra::Shader::IpaInterpMode::Linear:
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if (stage == Maxwell3D::Regs::ShaderStage::Fragment &&
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attribute.index == Attribute::Index::Position) {
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switch (attribute.element) {
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case 0:
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shader.AddLine(regs.GetRegisterAsFloat(reg) + " = gl_FragCoord.x;");
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break;
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case 1:
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shader.AddLine(regs.GetRegisterAsFloat(reg) + " = gl_FragCoord.y;");
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break;
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case 2:
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shader.AddLine(regs.GetRegisterAsFloat(reg) + " = gl_FragCoord.z;");
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break;
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case 3:
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shader.AddLine(regs.GetRegisterAsFloat(reg) + " = 1.0;");
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break;
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}
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} else {
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regs.SetRegisterToInputAttibute(reg, attribute.element, attribute.index);
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}
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break;
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case Tegra::Shader::IpaInterpMode::Perspective:
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regs.SetRegisterToInputAttibute(reg, attribute.element, attribute.index);
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break;
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default:
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LOG_CRITICAL(HW_GPU, "Unhandled IPA mode: {}",
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static_cast<u32>(instr.ipa.interp_mode.Value()));
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UNREACHABLE();
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regs.SetRegisterToInputAttibute(reg, attribute.element, attribute.index);
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}
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Tegra::Shader::IpaMode input_mode{instr.ipa.interp_mode.Value(),
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instr.ipa.sample_mode.Value()};
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regs.SetRegisterToInputAttibute(reg, attribute.element, attribute.index,
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input_mode);
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break;
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}
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case OpCode::Id::SSY: {
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