shader_recompiler: Align SSBO offsets in GlobalMemory functions
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735612c9b3
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@ -5,6 +5,7 @@
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#include "shader_recompiler/backend/glasm/glasm_emit_context.h"
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#include "shader_recompiler/frontend/ir/program.h"
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#include "shader_recompiler/frontend/ir/value.h"
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#include "shader_recompiler/profile.h"
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#include "shader_recompiler/runtime_info.h"
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namespace Shader::Backend::GLASM {
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@ -35,7 +36,9 @@ void GlobalStorageOp(EmitContext& ctx, Register address, bool pointer_based, std
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continue;
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}
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const auto& ssbo{ctx.info.storage_buffers_descriptors[index]};
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ctx.Add("LDC.U64 DC.x,c{}[{}];" // ssbo_addr
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const u64 ssbo_align_mask{~(ctx.profile.min_ssbo_alignment - 1U)};
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ctx.Add("LDC.U64 DC.x,c{}[{}];" // unaligned_ssbo_addr
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"AND.U64 DC.x,DC.x,{};" // ssbo_addr = unaligned_ssbo_addr & ssbo_align_mask
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"LDC.U32 RC.x,c{}[{}];" // ssbo_size_u32
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"CVT.U64.U32 DC.y,RC.x;" // ssbo_size = ssbo_size_u32
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"ADD.U64 DC.y,DC.y,DC.x;" // ssbo_end = ssbo_addr + ssbo_size
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@ -44,8 +47,8 @@ void GlobalStorageOp(EmitContext& ctx, Register address, bool pointer_based, std
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"AND.U.CC RC.x,RC.x,RC.y;" // cond = a && b
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"IF NE.x;" // if cond
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"SUB.U64 DC.x,{}.x,DC.x;", // offset = input_addr - ssbo_addr
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ssbo.cbuf_index, ssbo.cbuf_offset, ssbo.cbuf_index, ssbo.cbuf_offset + 8, address,
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address, address);
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ssbo.cbuf_index, ssbo.cbuf_offset, ssbo_align_mask, ssbo.cbuf_index,
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ssbo.cbuf_offset + 8, address, address, address);
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if (pointer_based) {
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ctx.Add("PK64.U DC.y,c[{}];" // host_ssbo = cbuf
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"ADD.U64 DC.x,DC.x,DC.y;" // host_addr = host_ssbo + offset
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@ -601,7 +601,10 @@ std::string EmitContext::DefineGlobalMemoryFunctions() {
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addr_xy[i] = fmt::format("ftou({}[{}].{})", cbuf, addr_loc / 16, Swizzle(addr_loc));
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size_xy[i] = fmt::format("ftou({}[{}].{})", cbuf, size_loc / 16, Swizzle(size_loc));
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}
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const auto addr_pack{fmt::format("packUint2x32(uvec2({},{}))", addr_xy[0], addr_xy[1])};
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const u32 ssbo_align_mask{~(static_cast<u32>(profile.min_ssbo_alignment) - 1U)};
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const auto aligned_low_addr{fmt::format("{}&{}", addr_xy[0], ssbo_align_mask)};
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const auto aligned_addr{fmt::format("uvec2({},{})", aligned_low_addr, addr_xy[1])};
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const auto addr_pack{fmt::format("packUint2x32({})", aligned_addr)};
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const auto addr_statment{fmt::format("uint64_t {}={};", ssbo_addr, addr_pack)};
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func += addr_statment;
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@ -891,7 +891,9 @@ void EmitContext::DefineGlobalMemoryFunctions(const Info& info) {
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const Id ssbo_size_pointer{OpAccessChain(uniform_types.U32, cbufs[ssbo.cbuf_index].U32,
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zero, ssbo_size_cbuf_offset)};
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const Id ssbo_addr{OpBitcast(U64, OpLoad(U32[2], ssbo_addr_pointer))};
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const u64 ssbo_align_mask{~(profile.min_ssbo_alignment - 1U)};
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const Id unaligned_addr{OpBitcast(U64, OpLoad(U32[2], ssbo_addr_pointer))};
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const Id ssbo_addr{OpBitwiseAnd(U64, unaligned_addr, Constant(U64, ssbo_align_mask))};
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const Id ssbo_size{OpUConvert(U64, OpLoad(U32[1], ssbo_size_pointer))};
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const Id ssbo_end{OpIAdd(U64, ssbo_addr, ssbo_size)};
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const Id cond{OpLogicalAnd(U1, OpUGreaterThanEqual(U1, addr, ssbo_addr),
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@ -84,6 +84,8 @@ struct Profile {
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/// Maxwell and earlier nVidia architectures have broken robust support
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bool has_broken_robust{};
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u64 min_ssbo_alignment{};
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};
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} // namespace Shader
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@ -1796,7 +1796,8 @@ Binding BufferCache<P>::StorageBufferBinding(GPUVAddr ssbo_addr, u32 cbuf_index,
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return NULL_BINDING;
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}
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const std::optional<VAddr> cpu_addr = gpu_memory->GpuToCpuAddress(gpu_addr);
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ASSERT_MSG(cpu_addr, "Unaligned storage buffer address not found for cbuf index {}", cbuf_index);
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ASSERT_MSG(cpu_addr, "Unaligned storage buffer address not found for cbuf index {}",
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cbuf_index);
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// The end address used for size calculation does not need to be aligned
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const VAddr cpu_end = Common::AlignUp(*cpu_addr + size, Core::Memory::YUZU_PAGESIZE);
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@ -232,6 +232,7 @@ ShaderCache::ShaderCache(RasterizerOpenGL& rasterizer_, Core::Frontend::EmuWindo
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.has_gl_bool_ref_bug = device.HasBoolRefBug(),
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.ignore_nan_fp_comparisons = true,
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.gl_max_compute_smem_size = device.GetMaxComputeSharedMemorySize(),
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.min_ssbo_alignment = device.GetShaderStorageBufferAlignment(),
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},
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host_info{
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.support_float64 = true,
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@ -359,6 +359,7 @@ PipelineCache::PipelineCache(RasterizerVulkan& rasterizer_, const Device& device
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driver_id == VK_DRIVER_ID_QUALCOMM_PROPRIETARY,
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.has_broken_robust =
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device.IsNvidia() && device.GetNvidiaArch() <= NvidiaArchitecture::Arch_Pascal,
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.min_ssbo_alignment = device.GetStorageBufferAlignment(),
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};
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host_info = Shader::HostTranslateInfo{
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