yuzu-emu
/
yuzu-mainline
Archived
1
0
Fork 0

GPU: Implemented the ISETP_R and ISETP_C shader instructions.

This commit is contained in:
Subv 2018-06-04 11:12:03 -05:00
parent ba117854f9
commit 7c181fd4f4
2 changed files with 48 additions and 0 deletions

View File

@ -238,6 +238,16 @@ union Instruction {
BitField<56, 1, u64> neg_b; BitField<56, 1, u64> neg_b;
} fsetp; } fsetp;
union {
BitField<0, 3, u64> pred0;
BitField<3, 3, u64> pred3;
BitField<39, 3, u64> pred39;
BitField<42, 1, u64> neg_pred;
BitField<45, 2, PredOperation> op;
BitField<48, 1, u64> is_signed;
BitField<49, 3, PredCondition> cond;
} isetp;
union { union {
BitField<39, 3, u64> pred39; BitField<39, 3, u64> pred39;
BitField<42, 1, u64> neg_pred; BitField<42, 1, u64> neg_pred;

View File

@ -1017,6 +1017,44 @@ private:
} }
break; break;
} }
case OpCode::Type::IntegerSetPredicate: {
std::string op_a = regs.GetRegisterAsInteger(instr.gpr8, 0, instr.isetp.is_signed);
std::string op_b{};
ASSERT_MSG(!instr.is_b_imm, "ISETP_IMM not implemented");
if (instr.is_b_gpr) {
op_b += regs.GetRegisterAsInteger(instr.gpr20, 0, instr.isetp.is_signed);
} else {
// TODO(Subv): This family of instructions don't store to a GPR, but GetUniform
// needs to know the type of the output register.
op_b += regs.GetUniform(instr.uniform, instr.gpr0);
}
using Tegra::Shader::Pred;
// We can't use the constant predicate as destination.
ASSERT(instr.isetp.pred3 != static_cast<u64>(Pred::UnusedIndex));
std::string second_pred =
GetPredicateCondition(instr.isetp.pred39, instr.isetp.neg_pred != 0);
std::string comparator = GetPredicateComparison(instr.isetp.cond);
std::string combiner = GetPredicateCombiner(instr.isetp.op);
std::string predicate = '(' + op_a + ") " + comparator + " (" + op_b + ')';
// Set the primary predicate to the result of Predicate OP SecondPredicate
SetPredicate(instr.isetp.pred3,
'(' + predicate + ") " + combiner + " (" + second_pred + ')');
if (instr.isetp.pred0 != static_cast<u64>(Pred::UnusedIndex)) {
// Set the secondary predicate to the result of !Predicate OP SecondPredicate,
// if enabled
SetPredicate(instr.isetp.pred0,
"!(" + predicate + ") " + combiner + " (" + second_pred + ')');
}
break;
}
case OpCode::Type::FloatSet: { case OpCode::Type::FloatSet: {
std::string op_a = instr.fset.neg_a ? "-" : ""; std::string op_a = instr.fset.neg_a ? "-" : "";
op_a += regs.GetRegisterAsFloat(instr.gpr8); op_a += regs.GetRegisterAsFloat(instr.gpr8);