Shader_IR: Fix TLD4 and add Bindless Variant.
This commit fixes an issue where not all 4 results of tld4 were being written, the color component was defaulted to red, among other things. It also implements the bindless variant.
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9f93ad08a5
commit
9293c3a0f2
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@ -1237,6 +1237,32 @@ union Instruction {
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}
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} tld4;
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union {
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BitField<35, 1, u64> ndv_flag;
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BitField<49, 1, u64> nodep_flag;
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BitField<50, 1, u64> dc_flag;
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BitField<33, 2, u64> info;
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BitField<37, 2, u64> component;
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bool UsesMiscMode(TextureMiscMode mode) const {
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switch (mode) {
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case TextureMiscMode::NDV:
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return ndv_flag != 0;
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case TextureMiscMode::NODEP:
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return nodep_flag != 0;
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case TextureMiscMode::DC:
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return dc_flag != 0;
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case TextureMiscMode::AOFFI:
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return info == 1;
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case TextureMiscMode::PTP:
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return info == 2;
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default:
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break;
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}
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return false;
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}
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} tld4_b;
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union {
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BitField<49, 1, u64> nodep_flag;
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BitField<50, 1, u64> dc_flag;
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@ -1590,7 +1616,8 @@ public:
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TEXS, // Texture Fetch with scalar/non-vec4 source/destinations
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TLD, // Texture Load
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TLDS, // Texture Load with scalar/non-vec4 source/destinations
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TLD4, // Texture Load 4
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TLD4, // Texture Gather 4
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TLD4_B, // Texture Gather 4 Bindless
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TLD4S, // Texture Load 4 with scalar / non - vec4 source / destinations
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TMML_B, // Texture Mip Map Level
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TMML, // Texture Mip Map Level
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@ -1881,6 +1908,7 @@ private:
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INST("11011100--11----", Id::TLD, Type::Texture, "TLD"),
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INST("1101-01---------", Id::TLDS, Type::Texture, "TLDS"),
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INST("110010----111---", Id::TLD4, Type::Texture, "TLD4"),
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INST("1101111011111---", Id::TLD4_B, Type::Texture, "TLD4_B"),
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INST("1101111100------", Id::TLD4S, Type::Texture, "TLD4S"),
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INST("110111110110----", Id::TMML_B, Type::Texture, "TMML_B"),
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INST("1101111101011---", Id::TMML, Type::Texture, "TMML"),
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@ -96,6 +96,10 @@ u32 ShaderIR::DecodeTexture(NodeBlock& bb, u32 pc) {
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}
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break;
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}
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case OpCode::Id::TLD4_B: {
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is_bindless = true;
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[[fallthrough]];
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}
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case OpCode::Id::TLD4: {
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ASSERT(instr.tld4.array == 0);
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UNIMPLEMENTED_IF_MSG(instr.tld4.UsesMiscMode(TextureMiscMode::NDV),
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@ -108,11 +112,14 @@ u32 ShaderIR::DecodeTexture(NodeBlock& bb, u32 pc) {
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}
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const auto texture_type = instr.tld4.texture_type.Value();
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const bool depth_compare = instr.tld4.UsesMiscMode(TextureMiscMode::DC);
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const bool depth_compare = is_bindless ? instr.tld4_b.UsesMiscMode(TextureMiscMode::DC)
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: instr.tld4.UsesMiscMode(TextureMiscMode::DC);
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const bool is_array = instr.tld4.array != 0;
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const bool is_aoffi = instr.tld4.UsesMiscMode(TextureMiscMode::AOFFI);
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const bool is_aoffi = is_bindless ? instr.tld4_b.UsesMiscMode(TextureMiscMode::AOFFI)
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: instr.tld4.UsesMiscMode(TextureMiscMode::AOFFI);
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WriteTexInstructionFloat(
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bb, instr, GetTld4Code(instr, texture_type, depth_compare, is_array, is_aoffi));
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bb, instr,
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GetTld4Code(instr, texture_type, depth_compare, is_array, is_aoffi, is_bindless), true);
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break;
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}
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case OpCode::Id::TLD4S: {
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@ -359,10 +366,11 @@ const Sampler& ShaderIR::GetBindlessSampler(const Tegra::Shader::Register& reg,
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return *used_samplers.emplace(entry).first;
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}
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void ShaderIR::WriteTexInstructionFloat(NodeBlock& bb, Instruction instr, const Node4& components) {
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void ShaderIR::WriteTexInstructionFloat(NodeBlock& bb, Instruction instr, const Node4& components,
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bool is_tld4) {
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u32 dest_elem = 0;
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for (u32 elem = 0; elem < 4; ++elem) {
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if (!instr.tex.IsComponentEnabled(elem)) {
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if (!is_tld4 && !instr.tex.IsComponentEnabled(elem)) {
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// Skip disabled components
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continue;
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}
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@ -583,7 +591,7 @@ Node4 ShaderIR::GetTexsCode(Instruction instr, TextureType texture_type,
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}
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Node4 ShaderIR::GetTld4Code(Instruction instr, TextureType texture_type, bool depth_compare,
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bool is_array, bool is_aoffi) {
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bool is_array, bool is_aoffi, bool is_bindless) {
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const std::size_t coord_count = GetCoordCount(texture_type);
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// If enabled arrays index is always stored in the gpr8 field
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@ -597,6 +605,12 @@ Node4 ShaderIR::GetTld4Code(Instruction instr, TextureType texture_type, bool de
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}
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u64 parameter_register = instr.gpr20.Value();
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const auto& sampler =
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is_bindless
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? GetBindlessSampler(parameter_register++, {{texture_type, is_array, depth_compare}})
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: GetSampler(instr.sampler, {{texture_type, is_array, depth_compare}});
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std::vector<Node> aoffi;
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if (is_aoffi) {
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aoffi = GetAoffiCoordinates(GetRegister(parameter_register++), coord_count, true);
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@ -607,12 +621,14 @@ Node4 ShaderIR::GetTld4Code(Instruction instr, TextureType texture_type, bool de
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dc = GetRegister(parameter_register++);
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}
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const auto& sampler = GetSampler(instr.sampler, {{texture_type, is_array, depth_compare}});
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const Node component = is_bindless ? Immediate(static_cast<u32>(instr.tld4_b.component))
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: Immediate(static_cast<u32>(instr.tld4.component));
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Node4 values;
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for (u32 element = 0; element < values.size(); ++element) {
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auto coords_copy = coords;
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MetaTexture meta{sampler, GetRegister(array_register), dc, aoffi, {}, {}, {}, element};
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MetaTexture meta{sampler, GetRegister(array_register), dc, aoffi, {}, {}, component,
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element};
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values[element] = Operation(OperationCode::TextureGather, meta, std::move(coords_copy));
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}
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@ -326,7 +326,7 @@ private:
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Node BitfieldInsert(Node base, Node insert, u32 offset, u32 bits);
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void WriteTexInstructionFloat(NodeBlock& bb, Tegra::Shader::Instruction instr,
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const Node4& components);
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const Node4& components, bool is_tld4 = false);
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void WriteTexsInstructionFloat(NodeBlock& bb, Tegra::Shader::Instruction instr,
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const Node4& components, bool ignore_mask = false);
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@ -343,7 +343,7 @@ private:
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bool is_array);
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Node4 GetTld4Code(Tegra::Shader::Instruction instr, Tegra::Shader::TextureType texture_type,
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bool depth_compare, bool is_array, bool is_aoffi);
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bool depth_compare, bool is_array, bool is_aoffi, bool is_bindless);
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Node4 GetTldCode(Tegra::Shader::Instruction instr);
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