shader_decode: Implement SSY and SYNC
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@ -57,6 +57,25 @@ u32 ShaderIR::DecodeOther(BasicBlock& bb, u32 pc) {
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bb.push_back(Operation(OperationCode::Bra, Immediate(target)));
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bb.push_back(Operation(OperationCode::Bra, Immediate(target)));
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break;
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break;
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}
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}
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case OpCode::Id::SSY: {
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UNIMPLEMENTED_IF_MSG(instr.bra.constant_buffer != 0,
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"Constant buffer flow is not supported");
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// The SSY opcode tells the GPU where to re-converge divergent execution paths, it sets the
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// target of the jump that the SYNC instruction will make. The SSY opcode has a similar
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// structure to the BRA opcode.
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bb.push_back(Operation(OperationCode::Ssy, Immediate(pc + instr.bra.GetBranchTarget())));
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break;
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}
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case OpCode::Id::SYNC: {
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const Tegra::Shader::ConditionCode cc = instr.flow_condition_code;
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UNIMPLEMENTED_IF_MSG(cc != Tegra::Shader::ConditionCode::T, "SYNC condition code used: {}",
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static_cast<u32>(cc));
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// The SYNC opcode jumps to the address previously set by the SSY opcode
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bb.push_back(Operation(OperationCode::Sync));
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break;
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}
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case OpCode::Id::IPA: {
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case OpCode::Id::IPA: {
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const auto& attribute = instr.attribute.fmt28;
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const auto& attribute = instr.attribute.fmt28;
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const Tegra::Shader::IpaMode input_mode{instr.ipa.interp_mode.Value(),
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const Tegra::Shader::IpaMode input_mode{instr.ipa.interp_mode.Value(),
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