arm: General cleanup
- Remove several typedefs for ARMul_State. - Remove unused functions - Remove unused/unnecessary headers - Removed unused enums, etc.
This commit is contained in:
Lioncash
parent
9b69079c83
commit
a75e1ff6e6
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@ -2,7 +2,6 @@
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "core/arm/skyeye_common/arm_regformat.h"
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#include "core/arm/skyeye_common/armdefs.h"
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#include "core/arm/dyncom/arm_dyncom_dec.h"
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@ -5,23 +5,19 @@
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#define CITRA_IGNORE_EXIT(x)
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#include <algorithm>
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#include <unordered_map>
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#include <stdio.h>
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#include <assert.h>
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#include <cstdio>
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#include <vector>
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#include <unordered_map>
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using namespace std;
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#include "core/arm/skyeye_common/armdefs.h"
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#include "core/arm/skyeye_common/armmmu.h"
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#include "arm_dyncom_thumb.h"
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#include "arm_dyncom_run.h"
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#include "core/arm/skyeye_common/vfp/vfp.h"
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#include "core/arm/disassembler/arm_disasm.h"
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#include "common/logging/log.h"
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#include "core/mem_map.h"
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#include "core/hle/hle.h"
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#include "core/arm/disassembler/arm_disasm.h"
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#include "core/arm/dyncom/arm_dyncom_thumb.h"
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#include "core/arm/dyncom/arm_dyncom_run.h"
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#include "core/arm/skyeye_common/armdefs.h"
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#include "core/arm/skyeye_common/armmmu.h"
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#include "core/arm/skyeye_common/vfp/vfp.h"
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enum {
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COND = (1 << 0),
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@ -44,8 +40,7 @@ enum {
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#define ROTATE_RIGHT_32(n, i) ROTATE_RIGHT(n, i, 32)
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#define ROTATE_LEFT_32(n, i) ROTATE_LEFT(n, i, 32)
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typedef arm_core_t arm_processor;
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typedef unsigned int (*shtop_fp_t)(arm_processor *cpu, unsigned int sht_oper);
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typedef unsigned int (*shtop_fp_t)(ARMul_State* cpu, unsigned int sht_oper);
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// Defines a reservation granule of 2 words, which protects the first 2 words starting at the tag.
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// This is the smallest granule allowed by the v7 spec, and is coincidentally just large enough to
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@ -53,7 +48,7 @@ typedef unsigned int (*shtop_fp_t)(arm_processor *cpu, unsigned int sht_oper);
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static const ARMword RESERVATION_GRANULE_MASK = 0xFFFFFFF8;
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// Exclusive memory access
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static int exclusive_detect(ARMul_State* state, ARMword addr){
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static int exclusive_detect(ARMul_State* state, ARMword addr) {
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if(state->exclusive_tag == (addr & RESERVATION_GRANULE_MASK))
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return 0;
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else
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@ -69,7 +64,7 @@ static void remove_exclusive(ARMul_State* state, ARMword addr){
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state->exclusive_tag = 0xFFFFFFFF;
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}
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unsigned int DPO(Immediate)(arm_processor *cpu, unsigned int sht_oper) {
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unsigned int DPO(Immediate)(ARMul_State* cpu, unsigned int sht_oper) {
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unsigned int immed_8 = BITS(sht_oper, 0, 7);
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unsigned int rotate_imm = BITS(sht_oper, 8, 11);
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unsigned int shifter_operand = ROTATE_RIGHT_32(immed_8, rotate_imm * 2);
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@ -80,14 +75,14 @@ unsigned int DPO(Immediate)(arm_processor *cpu, unsigned int sht_oper) {
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return shifter_operand;
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}
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unsigned int DPO(Register)(arm_processor *cpu, unsigned int sht_oper) {
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unsigned int DPO(Register)(ARMul_State* cpu, unsigned int sht_oper) {
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unsigned int rm = CHECK_READ_REG15(cpu, RM);
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unsigned int shifter_operand = rm;
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cpu->shifter_carry_out = cpu->CFlag;
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return shifter_operand;
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}
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unsigned int DPO(LogicalShiftLeftByImmediate)(arm_processor *cpu, unsigned int sht_oper) {
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unsigned int DPO(LogicalShiftLeftByImmediate)(ARMul_State* cpu, unsigned int sht_oper) {
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int shift_imm = BITS(sht_oper, 7, 11);
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unsigned int rm = CHECK_READ_REG15(cpu, RM);
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unsigned int shifter_operand;
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@ -101,7 +96,7 @@ unsigned int DPO(LogicalShiftLeftByImmediate)(arm_processor *cpu, unsigned int s
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return shifter_operand;
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}
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unsigned int DPO(LogicalShiftLeftByRegister)(arm_processor *cpu, unsigned int sht_oper) {
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unsigned int DPO(LogicalShiftLeftByRegister)(ARMul_State* cpu, unsigned int sht_oper) {
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int shifter_operand;
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unsigned int rm = CHECK_READ_REG15(cpu, RM);
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unsigned int rs = CHECK_READ_REG15(cpu, RS);
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@ -121,7 +116,7 @@ unsigned int DPO(LogicalShiftLeftByRegister)(arm_processor *cpu, unsigned int sh
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return shifter_operand;
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}
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unsigned int DPO(LogicalShiftRightByImmediate)(arm_processor *cpu, unsigned int sht_oper) {
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unsigned int DPO(LogicalShiftRightByImmediate)(ARMul_State* cpu, unsigned int sht_oper) {
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unsigned int rm = CHECK_READ_REG15(cpu, RM);
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unsigned int shifter_operand;
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int shift_imm = BITS(sht_oper, 7, 11);
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@ -135,7 +130,7 @@ unsigned int DPO(LogicalShiftRightByImmediate)(arm_processor *cpu, unsigned int
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return shifter_operand;
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}
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unsigned int DPO(LogicalShiftRightByRegister)(arm_processor *cpu, unsigned int sht_oper) {
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unsigned int DPO(LogicalShiftRightByRegister)(ARMul_State* cpu, unsigned int sht_oper) {
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unsigned int rs = CHECK_READ_REG15(cpu, RS);
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unsigned int rm = CHECK_READ_REG15(cpu, RM);
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unsigned int shifter_operand;
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@ -155,7 +150,7 @@ unsigned int DPO(LogicalShiftRightByRegister)(arm_processor *cpu, unsigned int s
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return shifter_operand;
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}
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unsigned int DPO(ArithmeticShiftRightByImmediate)(arm_processor *cpu, unsigned int sht_oper) {
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unsigned int DPO(ArithmeticShiftRightByImmediate)(ARMul_State* cpu, unsigned int sht_oper) {
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unsigned int rm = CHECK_READ_REG15(cpu, RM);
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unsigned int shifter_operand;
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int shift_imm = BITS(sht_oper, 7, 11);
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@ -172,7 +167,7 @@ unsigned int DPO(ArithmeticShiftRightByImmediate)(arm_processor *cpu, unsigned i
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return shifter_operand;
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}
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unsigned int DPO(ArithmeticShiftRightByRegister)(arm_processor *cpu, unsigned int sht_oper) {
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unsigned int DPO(ArithmeticShiftRightByRegister)(ARMul_State* cpu, unsigned int sht_oper) {
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unsigned int rs = CHECK_READ_REG15(cpu, RS);
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unsigned int rm = CHECK_READ_REG15(cpu, RM);
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unsigned int shifter_operand;
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@ -192,7 +187,7 @@ unsigned int DPO(ArithmeticShiftRightByRegister)(arm_processor *cpu, unsigned in
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return shifter_operand;
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}
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unsigned int DPO(RotateRightByImmediate)(arm_processor *cpu, unsigned int sht_oper) {
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unsigned int DPO(RotateRightByImmediate)(ARMul_State* cpu, unsigned int sht_oper) {
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unsigned int shifter_operand;
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unsigned int rm = CHECK_READ_REG15(cpu, RM);
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int shift_imm = BITS(sht_oper, 7, 11);
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@ -206,7 +201,7 @@ unsigned int DPO(RotateRightByImmediate)(arm_processor *cpu, unsigned int sht_op
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return shifter_operand;
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}
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unsigned int DPO(RotateRightByRegister)(arm_processor *cpu, unsigned int sht_oper) {
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unsigned int DPO(RotateRightByRegister)(ARMul_State* cpu, unsigned int sht_oper) {
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unsigned int rm = CHECK_READ_REG15(cpu, RM);
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unsigned int rs = CHECK_READ_REG15(cpu, RS);
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unsigned int shifter_operand;
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@ -223,7 +218,7 @@ unsigned int DPO(RotateRightByRegister)(arm_processor *cpu, unsigned int sht_ope
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return shifter_operand;
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}
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typedef void (*get_addr_fp_t)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int rw);
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typedef void (*get_addr_fp_t)(ARMul_State *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int rw);
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typedef struct _ldst_inst {
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unsigned int inst;
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@ -231,7 +226,7 @@ typedef struct _ldst_inst {
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} ldst_inst;
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#define DEBUG_MSG LOG_DEBUG(Core_ARM11, "inst is %x", inst); CITRA_IGNORE_EXIT(0)
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int CondPassed(arm_processor *cpu, unsigned int cond);
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int CondPassed(ARMul_State* cpu, unsigned int cond);
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#define LnSWoUB(s) glue(LnSWoUB, s)
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#define MLnS(s) glue(MLnS, s)
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@ -243,7 +238,7 @@ int CondPassed(arm_processor *cpu, unsigned int cond);
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#define P_BIT BIT(inst, 24)
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#define OFFSET_12 BITS(inst, 0, 11)
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void LnSWoUB(ImmediateOffset)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int rw) {
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void LnSWoUB(ImmediateOffset)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) {
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unsigned int Rn = BITS(inst, 16, 19);
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unsigned int addr;
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@ -255,7 +250,7 @@ void LnSWoUB(ImmediateOffset)(arm_processor *cpu, unsigned int inst, unsigned in
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virt_addr = addr;
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}
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void LnSWoUB(RegisterOffset)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int rw) {
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void LnSWoUB(RegisterOffset)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) {
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unsigned int Rn = BITS(inst, 16, 19);
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unsigned int Rm = BITS(inst, 0, 3);
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unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn);
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@ -270,7 +265,7 @@ void LnSWoUB(RegisterOffset)(arm_processor *cpu, unsigned int inst, unsigned int
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virt_addr = addr;
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}
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void LnSWoUB(ImmediatePostIndexed)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int rw) {
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void LnSWoUB(ImmediatePostIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) {
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unsigned int Rn = BITS(inst, 16, 19);
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unsigned int addr = CHECK_READ_REG15_WA(cpu, Rn);
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@ -282,7 +277,7 @@ void LnSWoUB(ImmediatePostIndexed)(arm_processor *cpu, unsigned int inst, unsign
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virt_addr = addr;
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}
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void LnSWoUB(ImmediatePreIndexed)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int rw) {
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void LnSWoUB(ImmediatePreIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) {
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unsigned int Rn = BITS(inst, 16, 19);
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unsigned int addr;
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@ -297,7 +292,7 @@ void LnSWoUB(ImmediatePreIndexed)(arm_processor *cpu, unsigned int inst, unsigne
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cpu->Reg[Rn] = addr;
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}
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void MLnS(RegisterPreIndexed)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int rw) {
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void MLnS(RegisterPreIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) {
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unsigned int addr;
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unsigned int Rn = BITS(inst, 16, 19);
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unsigned int Rm = BITS(inst, 0, 3);
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@ -315,7 +310,7 @@ void MLnS(RegisterPreIndexed)(arm_processor *cpu, unsigned int inst, unsigned in
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cpu->Reg[Rn] = addr;
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}
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void LnSWoUB(RegisterPreIndexed)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int rw) {
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void LnSWoUB(RegisterPreIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) {
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unsigned int Rn = BITS(inst, 16, 19);
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unsigned int Rm = BITS(inst, 0, 3);
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unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn);
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@ -334,7 +329,7 @@ void LnSWoUB(RegisterPreIndexed)(arm_processor *cpu, unsigned int inst, unsigned
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}
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}
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void LnSWoUB(ScaledRegisterPreIndexed)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int rw) {
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void LnSWoUB(ScaledRegisterPreIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) {
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unsigned int shift = BITS(inst, 5, 6);
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unsigned int shift_imm = BITS(inst, 7, 11);
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unsigned int Rn = BITS(inst, 16, 19);
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@ -385,7 +380,7 @@ void LnSWoUB(ScaledRegisterPreIndexed)(arm_processor *cpu, unsigned int inst, un
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cpu->Reg[Rn] = addr;
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}
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void LnSWoUB(ScaledRegisterPostIndexed)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int rw) {
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void LnSWoUB(ScaledRegisterPostIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) {
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unsigned int shift = BITS(inst, 5, 6);
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unsigned int shift_imm = BITS(inst, 7, 11);
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unsigned int Rn = BITS(inst, 16, 19);
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@ -434,7 +429,7 @@ void LnSWoUB(ScaledRegisterPostIndexed)(arm_processor *cpu, unsigned int inst, u
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}
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}
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void LnSWoUB(RegisterPostIndexed)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int rw) {
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void LnSWoUB(RegisterPostIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) {
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unsigned int Rn = BITS(inst, 16, 19);
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unsigned int Rm = BITS(inst, 0, 3);
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unsigned int rm = CHECK_READ_REG15_WA(cpu, Rm);
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@ -450,7 +445,7 @@ void LnSWoUB(RegisterPostIndexed)(arm_processor *cpu, unsigned int inst, unsigne
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}
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}
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void MLnS(ImmediateOffset)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int rw) {
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void MLnS(ImmediateOffset)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) {
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unsigned int immedL = BITS(inst, 0, 3);
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unsigned int immedH = BITS(inst, 8, 11);
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unsigned int Rn = BITS(inst, 16, 19);
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@ -466,7 +461,7 @@ void MLnS(ImmediateOffset)(arm_processor *cpu, unsigned int inst, unsigned int &
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virt_addr = addr;
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}
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void MLnS(RegisterOffset)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int rw) {
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void MLnS(RegisterOffset)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) {
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unsigned int addr;
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unsigned int Rn = BITS(inst, 16, 19);
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unsigned int Rm = BITS(inst, 0, 3);
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@ -481,7 +476,7 @@ void MLnS(RegisterOffset)(arm_processor *cpu, unsigned int inst, unsigned int &v
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virt_addr = addr;
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}
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void MLnS(ImmediatePreIndexed)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int rw) {
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void MLnS(ImmediatePreIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) {
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unsigned int Rn = BITS(inst, 16, 19);
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unsigned int immedH = BITS(inst, 8, 11);
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unsigned int immedL = BITS(inst, 0, 3);
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@ -500,7 +495,7 @@ void MLnS(ImmediatePreIndexed)(arm_processor *cpu, unsigned int inst, unsigned i
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cpu->Reg[Rn] = addr;
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}
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void MLnS(ImmediatePostIndexed)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int rw) {
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void MLnS(ImmediatePostIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) {
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unsigned int Rn = BITS(inst, 16, 19);
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unsigned int immedH = BITS(inst, 8, 11);
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unsigned int immedL = BITS(inst, 0, 3);
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@ -519,7 +514,7 @@ void MLnS(ImmediatePostIndexed)(arm_processor *cpu, unsigned int inst, unsigned
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}
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}
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void MLnS(RegisterPostIndexed)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int rw) {
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void MLnS(RegisterPostIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) {
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unsigned int Rn = BITS(inst, 16, 19);
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unsigned int Rm = BITS(inst, 0, 3);
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unsigned int rm = CHECK_READ_REG15_WA(cpu, Rm);
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@ -534,7 +529,7 @@ void MLnS(RegisterPostIndexed)(arm_processor *cpu, unsigned int inst, unsigned i
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}
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}
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void LdnStM(DecrementBefore)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int rw) {
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void LdnStM(DecrementBefore)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) {
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unsigned int Rn = BITS(inst, 16, 19);
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unsigned int i = BITS(inst, 0, 15);
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int count = 0;
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@ -550,7 +545,7 @@ void LdnStM(DecrementBefore)(arm_processor *cpu, unsigned int inst, unsigned int
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cpu->Reg[Rn] -= count * 4;
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}
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void LdnStM(IncrementBefore)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int rw) {
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void LdnStM(IncrementBefore)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) {
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unsigned int Rn = BITS(inst, 16, 19);
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unsigned int i = BITS(inst, 0, 15);
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int count = 0;
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@ -566,7 +561,7 @@ void LdnStM(IncrementBefore)(arm_processor *cpu, unsigned int inst, unsigned int
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cpu->Reg[Rn] += count * 4;
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}
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void LdnStM(IncrementAfter)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int rw) {
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void LdnStM(IncrementAfter)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) {
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unsigned int Rn = BITS(inst, 16, 19);
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unsigned int i = BITS(inst, 0, 15);
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int count = 0;
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@ -582,7 +577,7 @@ void LdnStM(IncrementAfter)(arm_processor *cpu, unsigned int inst, unsigned int
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cpu->Reg[Rn] += count * 4;
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}
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void LdnStM(DecrementAfter)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int rw) {
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void LdnStM(DecrementAfter)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) {
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unsigned int Rn = BITS(inst, 16, 19);
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unsigned int i = BITS(inst, 0, 15);
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int count = 0;
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@ -600,7 +595,7 @@ void LdnStM(DecrementAfter)(arm_processor *cpu, unsigned int inst, unsigned int
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}
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}
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void LnSWoUB(ScaledRegisterOffset)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int rw) {
|
||||
void LnSWoUB(ScaledRegisterOffset)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr, unsigned int rw) {
|
||||
unsigned int shift = BITS(inst, 5, 6);
|
||||
unsigned int shift_imm = BITS(inst, 7, 11);
|
||||
unsigned int Rn = BITS(inst, 16, 19);
|
||||
|
|
@ -1115,7 +1110,7 @@ inline void *AllocBuffer(unsigned int size) {
|
|||
return (void *)&inst_buf[start];
|
||||
}
|
||||
|
||||
int CondPassed(arm_processor *cpu, unsigned int cond) {
|
||||
int CondPassed(ARMul_State* cpu, unsigned int cond) {
|
||||
#define NFLAG cpu->NFlag
|
||||
#define ZFLAG cpu->ZFlag
|
||||
#define CFLAG cpu->CFlag
|
||||
|
|
@ -3469,13 +3464,13 @@ const transop_fp_t arm_instruction_trans[] = {
|
|||
};
|
||||
|
||||
typedef std::unordered_map<u32, int> bb_map;
|
||||
bb_map CreamCache;
|
||||
static bb_map CreamCache;
|
||||
|
||||
void insert_bb(unsigned int addr, int start) {
|
||||
static void insert_bb(unsigned int addr, int start) {
|
||||
CreamCache[addr] = start;
|
||||
}
|
||||
|
||||
int find_bb(unsigned int addr, int &start) {
|
||||
static int find_bb(unsigned int addr, int& start) {
|
||||
int ret = -1;
|
||||
bb_map::const_iterator it = CreamCache.find(addr);
|
||||
if (it != CreamCache.end()) {
|
||||
|
|
@ -3492,7 +3487,7 @@ enum {
|
|||
FETCH_FAILURE
|
||||
};
|
||||
|
||||
static tdstate decode_thumb_instr(arm_processor *cpu, uint32_t inst, addr_t addr, uint32_t *arm_inst, uint32_t* inst_size, ARM_INST_PTR* ptr_inst_base){
|
||||
static tdstate decode_thumb_instr(ARMul_State* cpu, uint32_t inst, addr_t addr, uint32_t* arm_inst, uint32_t* inst_size, ARM_INST_PTR* ptr_inst_base){
|
||||
// Check if in Thumb mode
|
||||
tdstate ret = thumb_translate (addr, inst, arm_inst, inst_size);
|
||||
if(ret == t_branch){
|
||||
|
|
@ -3555,24 +3550,7 @@ typedef struct instruction_set_encoding_item ISEITEM;
|
|||
|
||||
extern const ISEITEM arm_instruction[];
|
||||
|
||||
vector<uint64_t> code_page_set;
|
||||
|
||||
void flush_bb(uint32_t addr) {
|
||||
bb_map::iterator it;
|
||||
uint32_t start;
|
||||
|
||||
addr &= 0xfffff000;
|
||||
for (it = CreamCache.begin(); it != CreamCache.end(); ) {
|
||||
start = static_cast<uint32_t>(it->first);
|
||||
start &= 0xfffff000;
|
||||
if (start == addr) {
|
||||
CreamCache.erase(it++);
|
||||
} else
|
||||
++it;
|
||||
}
|
||||
}
|
||||
|
||||
int InterpreterTranslate(arm_processor *cpu, int &bb_start, addr_t addr) {
|
||||
int InterpreterTranslate(ARMul_State* cpu, int& bb_start, addr_t addr) {
|
||||
// Decode instruction, get index
|
||||
// Allocate memory and init InsCream
|
||||
// Go on next, until terminal instruction
|
||||
|
|
@ -3628,8 +3606,6 @@ translated:
|
|||
return KEEP_GOING;
|
||||
}
|
||||
|
||||
#define LOG_IN_CLR skyeye_printf_in_color
|
||||
|
||||
int clz(unsigned int x) {
|
||||
int n;
|
||||
if (x == 0) return (32);
|
||||
|
|
@ -3642,9 +3618,7 @@ int clz(unsigned int x) {
|
|||
return n;
|
||||
}
|
||||
|
||||
unsigned arm_dyncom_SWI (ARMul_State * state, ARMword number);
|
||||
|
||||
static bool InAPrivilegedMode(arm_core_t *core) {
|
||||
static bool InAPrivilegedMode(ARMul_State* core) {
|
||||
return (core->Mode != USER32MODE);
|
||||
}
|
||||
|
||||
|
|
@ -3904,7 +3878,7 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
|
|||
#define PC (cpu->Reg[15])
|
||||
#define CHECK_EXT_INT if (!cpu->NirqSig && !(cpu->Cpsr & 0x80)) goto END;
|
||||
|
||||
arm_processor *cpu = state;
|
||||
ARMul_State* cpu = state;
|
||||
|
||||
// GCC and Clang have a C++ extension to support a lookup table of labels. Otherwise, fallback
|
||||
// to a clunky switch statement.
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
|
||||
#include "core/arm/skyeye_common/armdefs.h"
|
||||
|
||||
void switch_mode(arm_core_t *core, uint32_t mode) {
|
||||
void switch_mode(ARMul_State* core, uint32_t mode) {
|
||||
if (core->Mode == mode)
|
||||
return;
|
||||
|
||||
|
|
|
|||
|
|
@ -18,10 +18,10 @@
|
|||
|
||||
#pragma once
|
||||
|
||||
void switch_mode(arm_core_t *core, uint32_t mode);
|
||||
void switch_mode(ARMul_State* core, uint32_t mode);
|
||||
|
||||
/* FIXME, we temporarily think thumb instruction is always 16 bit */
|
||||
static inline u32 GET_INST_SIZE(arm_core_t* core) {
|
||||
static inline u32 GET_INST_SIZE(ARMul_State* core) {
|
||||
return core->TFlag? 2 : 4;
|
||||
}
|
||||
|
||||
|
|
@ -33,7 +33,7 @@ static inline u32 GET_INST_SIZE(arm_core_t* core) {
|
|||
*
|
||||
* @return
|
||||
*/
|
||||
static inline addr_t CHECK_READ_REG15_WA(arm_core_t* core, int Rn) {
|
||||
static inline addr_t CHECK_READ_REG15_WA(ARMul_State* core, int Rn) {
|
||||
return (Rn == 15)? ((core->Reg[15] & ~0x3) + GET_INST_SIZE(core) * 2) : core->Reg[Rn];
|
||||
}
|
||||
|
||||
|
|
@ -45,6 +45,6 @@ static inline addr_t CHECK_READ_REG15_WA(arm_core_t* core, int Rn) {
|
|||
*
|
||||
* @return
|
||||
*/
|
||||
static inline u32 CHECK_READ_REG15(arm_core_t* core, int Rn) {
|
||||
static inline u32 CHECK_READ_REG15(ARMul_State* core, int Rn) {
|
||||
return (Rn == 15)? ((core->Reg[15] & ~0x1) + GET_INST_SIZE(core) * 2) : core->Reg[Rn];
|
||||
}
|
||||
|
|
|
|||
|
|
@ -5,27 +5,17 @@
|
|||
// We can provide simple Thumb simulation by decoding the Thumb instruction into its corresponding
|
||||
// ARM instruction, and using the existing ARM simulator.
|
||||
|
||||
#include "core/arm/skyeye_common/skyeye_defs.h"
|
||||
|
||||
#ifndef MODET // Required for the Thumb instruction support
|
||||
#if 1
|
||||
#error "MODET needs to be defined for the Thumb world to work"
|
||||
#else
|
||||
#define MODET (1)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#include "core/arm/skyeye_common/armos.h"
|
||||
#include "core/arm/dyncom/arm_dyncom_thumb.h"
|
||||
#include "core/arm/skyeye_common/armos.h"
|
||||
#include "core/arm/skyeye_common/skyeye_defs.h"
|
||||
|
||||
// Decode a 16bit Thumb instruction. The instruction is in the low 16-bits of the tinstr field,
|
||||
// with the following Thumb instruction held in the high 16-bits. Passing in two Thumb instructions
|
||||
// allows easier simulation of the special dual BL instruction.
|
||||
|
||||
tdstate thumb_translate (addr_t addr, uint32_t instr, uint32_t* ainstr, uint32_t* inst_size) {
|
||||
tdstate thumb_translate(addr_t addr, uint32_t instr, uint32_t* ainstr, uint32_t* inst_size) {
|
||||
tdstate valid = t_uninitialized;
|
||||
ARMword tinstr;
|
||||
tinstr = instr;
|
||||
ARMword tinstr = instr;
|
||||
|
||||
// The endian should be judge here
|
||||
if((addr & 0x3) != 0)
|
||||
|
|
|
|||
|
|
@ -15,6 +15,7 @@
|
|||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
|
||||
|
||||
#include <cstring>
|
||||
#include "core/arm/skyeye_common/armdefs.h"
|
||||
#include "core/arm/skyeye_common/armemu.h"
|
||||
|
||||
|
|
@ -23,7 +24,7 @@
|
|||
\***************************************************************************/
|
||||
ARMul_State* ARMul_NewState(ARMul_State* state)
|
||||
{
|
||||
memset (state, 0, sizeof (ARMul_State));
|
||||
memset(state, 0, sizeof(ARMul_State));
|
||||
|
||||
state->Emulate = RUN;
|
||||
for (unsigned int i = 0; i < 16; i++) {
|
||||
|
|
|
|||
|
|
@ -16,9 +16,6 @@
|
|||
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
|
||||
|
||||
#include "core/arm/skyeye_common/armdefs.h"
|
||||
#include "core/arm/skyeye_common/armemu.h"
|
||||
#include "core/arm/disassembler/arm_disasm.h"
|
||||
#include "core/mem_map.h"
|
||||
|
||||
// Unsigned sum of absolute difference
|
||||
u8 ARMul_UnsignedAbsoluteDifference(u8 left, u8 right)
|
||||
|
|
|
|||
|
|
@ -17,19 +17,9 @@
|
|||
|
||||
#pragma once
|
||||
|
||||
#include <cerrno>
|
||||
#include <csignal>
|
||||
#include <cstdio>
|
||||
#include <cstdlib>
|
||||
#include <cstring>
|
||||
#include <fcntl.h>
|
||||
#include <sys/stat.h>
|
||||
#include <sys/types.h>
|
||||
|
||||
#include "arm_regformat.h"
|
||||
#include "common/common_types.h"
|
||||
#include "common/platform.h"
|
||||
#include "core/arm/skyeye_common/armmmu.h"
|
||||
#include "core/arm/skyeye_common/arm_regformat.h"
|
||||
#include "core/arm/skyeye_common/skyeye_defs.h"
|
||||
|
||||
#define BITS(s, a, b) ((s << ((sizeof(s) * 8 - 1) - b)) >> (sizeof(s) * 8 - b + a - 1))
|
||||
|
|
@ -118,9 +108,7 @@ struct ARMul_State
|
|||
// Add armv6 flags dyf:2010-08-09
|
||||
ARMword GEFlag, EFlag, AFlag, QFlag;
|
||||
|
||||
#ifdef MODET
|
||||
ARMword TFlag; // Thumb state
|
||||
#endif
|
||||
|
||||
unsigned long long NumInstrs; // The number of instructions executed
|
||||
unsigned NumInstrsToExecute;
|
||||
|
|
@ -218,8 +206,6 @@ So, if lateabtSig=1, then it means Late Abort Model(Base Updated Abort Model)
|
|||
u32 CurrWrite;
|
||||
};
|
||||
|
||||
typedef ARMul_State arm_core_t;
|
||||
|
||||
/***************************************************************************\
|
||||
* Types of ARM we know about *
|
||||
\***************************************************************************/
|
||||
|
|
|
|||
|
|
@ -19,61 +19,24 @@
|
|||
|
||||
#include "core/arm/skyeye_common/armdefs.h"
|
||||
|
||||
/* Macros to twiddle the status flags and mode. */
|
||||
#define NBIT ((unsigned)1L << 31)
|
||||
#define ZBIT (1L << 30)
|
||||
#define CBIT (1L << 29)
|
||||
#define VBIT (1L << 28)
|
||||
#define QBIT (1L << 27)
|
||||
#define IBIT (1L << 7)
|
||||
#define FBIT (1L << 6)
|
||||
#define IFBITS (3L << 6)
|
||||
#define R15IBIT (1L << 27)
|
||||
#define R15FBIT (1L << 26)
|
||||
#define R15IFBITS (3L << 26)
|
||||
// Flags for use with the APSR.
|
||||
enum : u32 {
|
||||
NBIT = (1U << 31U),
|
||||
ZBIT = (1 << 30),
|
||||
CBIT = (1 << 29),
|
||||
VBIT = (1 << 28),
|
||||
QBIT = (1 << 27),
|
||||
JBIT = (1 << 24),
|
||||
EBIT = (1 << 9),
|
||||
ABIT = (1 << 8),
|
||||
IBIT = (1 << 7),
|
||||
FBIT = (1 << 6),
|
||||
TBIT = (1 << 5),
|
||||
|
||||
#if defined MODE32 || defined MODET
|
||||
#define CCBITS (0xf8000000L)
|
||||
#else
|
||||
#define CCBITS (0xf0000000L)
|
||||
#endif
|
||||
|
||||
#define INTBITS (0xc0L)
|
||||
|
||||
#if defined MODET && defined MODE32
|
||||
#define PCBITS (0xffffffffL)
|
||||
#else
|
||||
#define PCBITS (0xfffffffcL)
|
||||
#endif
|
||||
|
||||
#define MODEBITS (0x1fL)
|
||||
#define R15INTBITS (3L << 26)
|
||||
|
||||
#if defined MODET && defined MODE32
|
||||
#define R15PCBITS (0x03ffffffL)
|
||||
#else
|
||||
#define R15PCBITS (0x03fffffcL)
|
||||
#endif
|
||||
|
||||
#define R15MODEBITS (0x3L)
|
||||
|
||||
#ifdef MODE32
|
||||
#define PCMASK PCBITS
|
||||
#define PCWRAP(pc) (pc)
|
||||
#else
|
||||
#define PCMASK R15PCBITS
|
||||
#define PCWRAP(pc) ((pc) & R15PCBITS)
|
||||
#endif
|
||||
|
||||
#define PC (state->Reg[15] & PCMASK)
|
||||
#define R15CCINTMODE (state->Reg[15] & (CCBITS | R15INTBITS | R15MODEBITS))
|
||||
#define R15INT (state->Reg[15] & R15INTBITS)
|
||||
#define R15INTPC (state->Reg[15] & (R15INTBITS | R15PCBITS))
|
||||
#define R15INTPCMODE (state->Reg[15] & (R15INTBITS | R15PCBITS | R15MODEBITS))
|
||||
#define R15INTMODE (state->Reg[15] & (R15INTBITS | R15MODEBITS))
|
||||
#define R15PC (state->Reg[15] & R15PCBITS)
|
||||
#define R15PCMODE (state->Reg[15] & (R15PCBITS | R15MODEBITS))
|
||||
#define R15MODE (state->Reg[15] & R15MODEBITS)
|
||||
// Masks for groups of bits in the APSR.
|
||||
MODEBITS = 0x1F,
|
||||
INTBITS = 0xC0,
|
||||
};
|
||||
|
||||
// Different ways to start the next instruction.
|
||||
enum {
|
||||
|
|
|
|||
|
|
@ -1,57 +1,38 @@
|
|||
#pragma once
|
||||
|
||||
#include "common/common.h"
|
||||
#include "common/common_types.h"
|
||||
|
||||
#define MODE32
|
||||
#define MODET
|
||||
|
||||
typedef struct
|
||||
struct cpu_config_t
|
||||
{
|
||||
const char *cpu_arch_name; /* CPU architecture version name.e.g. armv4t */
|
||||
const char *cpu_name; /* CPU name. e.g. arm7tdmi or arm720t */
|
||||
u32 cpu_val; /*CPU value; also call MMU ID or processor id;see
|
||||
ARM Architecture Reference Manual B2-6 */
|
||||
u32 cpu_mask; /* cpu_val's mask. */
|
||||
u32 cachetype; /* this CPU has what kind of cache */
|
||||
} cpu_config_t;
|
||||
const char* cpu_arch_name; // CPU architecture version name.e.g. ARMv4T
|
||||
const char* cpu_name; // CPU name. e.g. ARM7TDMI or ARM720T
|
||||
u32 cpu_val; // CPU value; also call MMU ID or processor id;see
|
||||
// ARM Architecture Reference Manual B2-6
|
||||
u32 cpu_mask; // cpu_val's mask.
|
||||
u32 cachetype; // CPU cache type
|
||||
};
|
||||
|
||||
typedef enum {
|
||||
/* No exception */
|
||||
No_exp = 0,
|
||||
/* Memory allocation exception */
|
||||
Malloc_exp,
|
||||
/* File open exception */
|
||||
File_open_exp,
|
||||
/* DLL open exception */
|
||||
Dll_open_exp,
|
||||
/* Invalid argument exception */
|
||||
Invarg_exp,
|
||||
/* Invalid module exception */
|
||||
Invmod_exp,
|
||||
/* wrong format exception for config file parsing */
|
||||
Conf_format_exp,
|
||||
/* some reference excess the predefiend range. Such as the index out of array range */
|
||||
Excess_range_exp,
|
||||
/* Can not find the desirable result */
|
||||
Not_found_exp,
|
||||
|
||||
/* Unknown exception */
|
||||
Unknown_exp
|
||||
} exception_t;
|
||||
|
||||
typedef enum {
|
||||
Align = 0,
|
||||
UnAlign
|
||||
} align_t;
|
||||
|
||||
typedef enum {
|
||||
Little_endian = 0,
|
||||
Big_endian
|
||||
} endian_t;
|
||||
|
||||
typedef enum {
|
||||
Phys_addr = 0,
|
||||
Virt_addr
|
||||
} addr_type_t;
|
||||
enum {
|
||||
// No exception
|
||||
No_exp = 0,
|
||||
// Memory allocation exception
|
||||
Malloc_exp,
|
||||
// File open exception
|
||||
File_open_exp,
|
||||
// DLL open exception
|
||||
Dll_open_exp,
|
||||
// Invalid argument exception
|
||||
Invarg_exp,
|
||||
// Invalid module exception
|
||||
Invmod_exp,
|
||||
// wrong format exception for config file parsing
|
||||
Conf_format_exp,
|
||||
// some reference excess the predefiend range. Such as the index out of array range
|
||||
Excess_range_exp,
|
||||
// Can not find the desirable result
|
||||
Not_found_exp,
|
||||
// Unknown exception
|
||||
Unknown_exp
|
||||
};
|
||||
|
||||
typedef u32 addr_t;
|
||||
|
|
|
|||
|
|
@ -21,6 +21,7 @@
|
|||
/* Note: this file handles interface with arm core and vfp registers */
|
||||
|
||||
#include "common/common.h"
|
||||
#include "common/logging/log.h"
|
||||
|
||||
#include "core/arm/skyeye_common/armdefs.h"
|
||||
#include "core/arm/skyeye_common/vfp/asm_vfp.h"
|
||||
|
|
@ -724,26 +725,26 @@ void VMOVR(ARMul_State* state, ARMword single, ARMword d, ARMword m)
|
|||
}
|
||||
|
||||
/* Miscellaneous functions */
|
||||
int32_t vfp_get_float(arm_core_t* state, unsigned int reg)
|
||||
int32_t vfp_get_float(ARMul_State* state, unsigned int reg)
|
||||
{
|
||||
LOG_TRACE(Core_ARM11, "VFP get float: s%d=[%08x]\n", reg, state->ExtReg[reg]);
|
||||
return state->ExtReg[reg];
|
||||
}
|
||||
|
||||
void vfp_put_float(arm_core_t* state, int32_t val, unsigned int reg)
|
||||
void vfp_put_float(ARMul_State* state, int32_t val, unsigned int reg)
|
||||
{
|
||||
LOG_TRACE(Core_ARM11, "VFP put float: s%d <= [%08x]\n", reg, val);
|
||||
state->ExtReg[reg] = val;
|
||||
}
|
||||
|
||||
uint64_t vfp_get_double(arm_core_t* state, unsigned int reg)
|
||||
uint64_t vfp_get_double(ARMul_State* state, unsigned int reg)
|
||||
{
|
||||
uint64_t result = ((uint64_t) state->ExtReg[reg*2+1])<<32 | state->ExtReg[reg*2];
|
||||
LOG_TRACE(Core_ARM11, "VFP get double: s[%d-%d]=[%016llx]\n", reg * 2 + 1, reg * 2, result);
|
||||
return result;
|
||||
}
|
||||
|
||||
void vfp_put_double(arm_core_t* state, uint64_t val, unsigned int reg)
|
||||
void vfp_put_double(ARMul_State* state, uint64_t val, unsigned int reg)
|
||||
{
|
||||
LOG_TRACE(Core_ARM11, "VFP put double: s[%d-%d] <= [%08x-%08x]\n", reg * 2 + 1, reg * 2, (uint32_t)(val >> 32), (uint32_t)(val & 0xffffffff));
|
||||
state->ExtReg[reg*2] = (uint32_t) (val & 0xffffffff);
|
||||
|
|
|
|||
|
|
@ -32,11 +32,7 @@
|
|||
|
||||
#pragma once
|
||||
|
||||
/* Custom edit */
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
|
||||
#include <cstdio>
|
||||
#include "common/common_types.h"
|
||||
#include "core/arm/skyeye_common/armdefs.h"
|
||||
|
||||
|
|
|
|||
|
|
@ -51,6 +51,7 @@
|
|||
* ===========================================================================
|
||||
*/
|
||||
|
||||
#include "common/logging/log.h"
|
||||
#include "core/arm/skyeye_common/vfp/vfp.h"
|
||||
#include "core/arm/skyeye_common/vfp/vfp_helper.h"
|
||||
#include "core/arm/skyeye_common/vfp/asm_vfp.h"
|
||||
|
|
|
|||
Reference in New Issue