dma_pushbuffer: Optimize to avoid loop and copy on Push.
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c568f5cea7
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@ -128,11 +128,9 @@ u32 nvhost_gpu::AllocateObjectContext(const std::vector<u8>& input, std::vector<
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return 0;
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}
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static void PushGPUEntries(const std::vector<Tegra::CommandListHeader>& entries) {
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static void PushGPUEntries(Tegra::CommandList&& entries) {
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auto& dma_pusher{Core::System::GetInstance().GPU().DmaPusher()};
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for (const auto& entry : entries) {
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dma_pusher.Push(entry);
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}
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dma_pusher.Push(std::move(entries));
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dma_pusher.DispatchCalls();
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}
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@ -149,11 +147,11 @@ u32 nvhost_gpu::SubmitGPFIFO(const std::vector<u8>& input, std::vector<u8>& outp
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params.num_entries * sizeof(Tegra::CommandListHeader),
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"Incorrect input size");
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std::vector<Tegra::CommandListHeader> entries(params.num_entries);
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Tegra::CommandList entries(params.num_entries);
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std::memcpy(entries.data(), &input[sizeof(IoctlSubmitGpfifo)],
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params.num_entries * sizeof(Tegra::CommandListHeader));
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PushGPUEntries(entries);
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PushGPUEntries(std::move(entries));
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params.fence_out.id = 0;
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params.fence_out.value = 0;
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@ -170,11 +168,11 @@ u32 nvhost_gpu::KickoffPB(const std::vector<u8>& input, std::vector<u8>& output)
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LOG_WARNING(Service_NVDRV, "(STUBBED) called, gpfifo={:X}, num_entries={:X}, flags={:X}",
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params.address, params.num_entries, params.flags);
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std::vector<Tegra::CommandListHeader> entries(params.num_entries);
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Tegra::CommandList entries(params.num_entries);
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Memory::ReadBlock(params.address, entries.data(),
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params.num_entries * sizeof(Tegra::CommandListHeader));
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PushGPUEntries(entries);
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PushGPUEntries(std::move(entries));
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params.fence_out.id = 0;
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params.fence_out.value = 0;
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@ -23,6 +23,8 @@ void DmaPusher::DispatchCalls() {
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// On entering GPU code, assume all memory may be touched by the ARM core.
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gpu.Maxwell3D().dirty_flags.OnMemoryWrite();
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dma_pushbuffer_subindex = 0;
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while (Core::System::GetInstance().IsPoweredOn()) {
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if (!Step()) {
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break;
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@ -89,11 +91,17 @@ bool DmaPusher::Step() {
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}
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} else if (ib_enable && !dma_pushbuffer.empty()) {
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// Current pushbuffer empty, but we have more IB entries to read
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const CommandListHeader& command_list_header{dma_pushbuffer.front()};
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const CommandList& command_list{dma_pushbuffer.front()};
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const CommandListHeader& command_list_header{command_list[dma_pushbuffer_subindex++]};
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dma_get = command_list_header.addr;
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dma_put = dma_get + command_list_header.size * sizeof(u32);
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non_main = command_list_header.is_non_main;
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dma_pushbuffer.pop();
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if (dma_pushbuffer_subindex >= command_list.size()) {
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// We've gone through the current list, remove it from the queue
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dma_pushbuffer.pop();
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dma_pushbuffer_subindex = 0;
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}
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} else {
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// Otherwise, pushbuffer empty and IB empty or nonexistent - nothing to do
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return {};
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@ -4,6 +4,7 @@
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#pragma once
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#include <vector>
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#include <queue>
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#include "common/bit_field.h"
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@ -45,6 +46,8 @@ static_assert(sizeof(CommandHeader) == sizeof(u32), "CommandHeader has incorrect
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class GPU;
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using CommandList = std::vector<Tegra::CommandListHeader>;
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/**
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* The DmaPusher class implements DMA submission to FIFOs, providing an area of memory that the
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* emulated app fills with commands and tells PFIFO to process. The pushbuffers are then assembled
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@ -57,8 +60,8 @@ public:
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explicit DmaPusher(GPU& gpu);
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~DmaPusher();
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void Push(const CommandListHeader& command_list_header) {
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dma_pushbuffer.push(command_list_header);
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void Push(CommandList&& entries) {
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dma_pushbuffer.push(std::move(entries));
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}
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void DispatchCalls();
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@ -72,7 +75,8 @@ private:
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GPU& gpu;
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std::queue<CommandListHeader> dma_pushbuffer;
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std::queue<CommandList> dma_pushbuffer; ///< Queue of command lists to be processed
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std::size_t dma_pushbuffer_subindex{}; ///< Index within a command list within the pushbuffer
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struct DmaState {
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u32 method; ///< Current method
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