GPU: Added registers for the number of vertices to render.
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0b3ab30762
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ae28a52277
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@ -83,7 +83,14 @@ public:
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}
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} rt[NumRenderTargets];
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INSERT_PADDING_WORDS(0x178);
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INSERT_PADDING_WORDS(0xDD);
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struct {
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u32 first;
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u32 count;
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} vertex_buffer;
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INSERT_PADDING_WORDS(0x99);
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struct {
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u32 address_high;
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@ -146,7 +153,10 @@ public:
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INSERT_PADDING_WORDS(1);
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struct {
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u32 vertex_end_gl;
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u32 vertex_begin_gl;
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union {
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u32 vertex_begin_gl;
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BitField<0, 16, u32> topology;
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};
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} draw;
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INSERT_PADDING_WORDS(0x139);
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struct {
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@ -336,6 +346,7 @@ private:
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"Field " #field_name " has invalid position")
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ASSERT_REG_POSITION(rt, 0x200);
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ASSERT_REG_POSITION(vertex_buffer, 0x35D);
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ASSERT_REG_POSITION(zeta, 0x3F8);
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ASSERT_REG_POSITION(rt_control, 0x487);
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ASSERT_REG_POSITION(tsc, 0x557);
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