Merge pull request #1273 from Subv/ld_sizes
Shaders: Implemented multiple-word loads and stores to and from attribute memory.
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commit
ba480ea2fb
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@ -67,6 +67,13 @@ private:
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u64 value{};
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};
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enum class AttributeSize : u64 {
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Word = 0,
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DoubleWord = 1,
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TripleWord = 2,
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QuadWord = 3,
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};
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union Attribute {
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Attribute() = default;
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@ -87,9 +94,10 @@ union Attribute {
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};
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union {
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BitField<20, 10, u64> immediate;
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BitField<22, 2, u64> element;
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BitField<24, 6, Index> index;
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BitField<47, 3, u64> size;
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BitField<47, 3, AttributeSize> size;
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} fmt20;
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union {
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@ -1772,13 +1772,34 @@ private:
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case OpCode::Type::Memory: {
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switch (opcode->GetId()) {
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case OpCode::Id::LD_A: {
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ASSERT_MSG(instr.attribute.fmt20.size == 0, "untested");
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// Note: Shouldn't this be interp mode flat? As in no interpolation made.
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ASSERT_MSG(instr.gpr8.Value() == Register::ZeroIndex,
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"Indirect attribute loads are not supported");
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ASSERT_MSG((instr.attribute.fmt20.immediate.Value() % sizeof(u32)) == 0,
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"Unaligned attribute loads are not supported");
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Tegra::Shader::IpaMode input_mode{Tegra::Shader::IpaInterpMode::Perspective,
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Tegra::Shader::IpaSampleMode::Default};
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regs.SetRegisterToInputAttibute(instr.gpr0, instr.attribute.fmt20.element,
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instr.attribute.fmt20.index, input_mode);
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u32 next_element = instr.attribute.fmt20.element;
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u32 next_index = static_cast<u32>(instr.attribute.fmt20.index.Value());
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const auto LoadNextElement = [&](u32 reg_offset) {
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regs.SetRegisterToInputAttibute(instr.gpr0.Value() + reg_offset, next_element,
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static_cast<Attribute::Index>(next_index),
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input_mode);
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// Load the next attribute element into the following register. If the element
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// to load goes beyond the vec4 size, load the first element of the next
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// attribute.
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next_element = (next_element + 1) % 4;
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next_index = next_index + (next_element == 0 ? 1 : 0);
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};
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const u32 num_words = static_cast<u32>(instr.attribute.fmt20.size.Value()) + 1;
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for (u32 reg_offset = 0; reg_offset < num_words; ++reg_offset) {
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LoadNextElement(reg_offset);
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}
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break;
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}
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case OpCode::Id::LD_C: {
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@ -1820,9 +1841,31 @@ private:
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break;
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}
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case OpCode::Id::ST_A: {
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ASSERT_MSG(instr.attribute.fmt20.size == 0, "untested");
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regs.SetOutputAttributeToRegister(instr.attribute.fmt20.index,
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instr.attribute.fmt20.element, instr.gpr0);
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ASSERT_MSG(instr.gpr8.Value() == Register::ZeroIndex,
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"Indirect attribute loads are not supported");
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ASSERT_MSG((instr.attribute.fmt20.immediate.Value() % sizeof(u32)) == 0,
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"Unaligned attribute loads are not supported");
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u32 next_element = instr.attribute.fmt20.element;
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u32 next_index = static_cast<u32>(instr.attribute.fmt20.index.Value());
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const auto StoreNextElement = [&](u32 reg_offset) {
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regs.SetOutputAttributeToRegister(static_cast<Attribute::Index>(next_index),
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next_element,
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instr.gpr0.Value() + reg_offset);
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// Load the next attribute element into the following register. If the element
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// to load goes beyond the vec4 size, load the first element of the next
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// attribute.
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next_element = (next_element + 1) % 4;
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next_index = next_index + (next_element == 0 ? 1 : 0);
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};
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const u32 num_words = static_cast<u32>(instr.attribute.fmt20.size.Value()) + 1;
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for (u32 reg_offset = 0; reg_offset < num_words; ++reg_offset) {
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StoreNextElement(reg_offset);
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}
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break;
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}
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case OpCode::Id::TEX: {
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