GPU: Emulate memory fills.
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0b4055c152
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@ -174,6 +174,14 @@ void TriggerCmdReqQueue(Service::Interface* self) {
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break;
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case GXCommandId::SET_MEMORY_FILL:
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GPU::Write<u32>(GPU::Registers::MemoryFillStart1, cmd_buff[1] >> 3);
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GPU::Write<u32>(GPU::Registers::MemoryFillEnd1, cmd_buff[3] >> 3);
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GPU::Write<u32>(GPU::Registers::MemoryFillSize1, cmd_buff[3] - cmd_buff[1]);
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GPU::Write<u32>(GPU::Registers::MemoryFillValue1, cmd_buff[2]);
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GPU::Write<u32>(GPU::Registers::MemoryFillStart2, cmd_buff[4] >> 3);
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GPU::Write<u32>(GPU::Registers::MemoryFillEnd2, cmd_buff[6] >> 3);
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GPU::Write<u32>(GPU::Registers::MemoryFillSize2, cmd_buff[6] - cmd_buff[4]);
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GPU::Write<u32>(GPU::Registers::MemoryFillValue2, cmd_buff[5]);
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break;
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// TODO: Check if texture copies are implemented correctly..
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@ -14,7 +14,7 @@ namespace GSP_GPU {
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enum class GXCommandId : u32 {
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REQUEST_DMA = 0x00000000,
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SET_COMMAND_LIST_LAST = 0x00000001,
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SET_MEMORY_FILL = 0x00000002, // TODO: Confirm? (lictru uses 0x01000102)
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SET_MEMORY_FILL = 0x01000102, // TODO: Confirm?
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SET_DISPLAY_TRANSFER = 0x00000003,
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SET_TEXTURE_COPY = 0x00000004,
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SET_COMMAND_LIST_FIRST = 0x00000005,
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@ -84,6 +84,26 @@ const u8* GetFramebufferPointer(const u32 address) {
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template <typename T>
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inline void Read(T &var, const u32 addr) {
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switch (addr) {
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case Registers::MemoryFillStart1:
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case Registers::MemoryFillStart2:
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var = g_regs.memory_fill[(addr - Registers::MemoryFillStart1) / 0x10].address_start;
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break;
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case Registers::MemoryFillEnd1:
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case Registers::MemoryFillEnd2:
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var = g_regs.memory_fill[(addr - Registers::MemoryFillEnd1) / 0x10].address_end;
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break;
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case Registers::MemoryFillSize1:
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case Registers::MemoryFillSize2:
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var = g_regs.memory_fill[(addr - Registers::MemoryFillSize1) / 0x10].size;
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break;
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case Registers::MemoryFillValue1:
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case Registers::MemoryFillValue2:
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var = g_regs.memory_fill[(addr - Registers::MemoryFillValue1) / 0x10].value;
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break;
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case Registers::FramebufferTopSize:
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var = g_regs.top_framebuffer.size;
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break;
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@ -194,6 +214,40 @@ inline void Read(T &var, const u32 addr) {
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template <typename T>
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inline void Write(u32 addr, const T data) {
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switch (static_cast<Registers::Id>(addr)) {
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case Registers::MemoryFillStart1:
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case Registers::MemoryFillStart2:
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g_regs.memory_fill[(addr - Registers::MemoryFillStart1) / 0x10].address_start = data;
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break;
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case Registers::MemoryFillEnd1:
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case Registers::MemoryFillEnd2:
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g_regs.memory_fill[(addr - Registers::MemoryFillEnd1) / 0x10].address_end = data;
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break;
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case Registers::MemoryFillSize1:
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case Registers::MemoryFillSize2:
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g_regs.memory_fill[(addr - Registers::MemoryFillSize1) / 0x10].size = data;
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break;
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case Registers::MemoryFillValue1:
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case Registers::MemoryFillValue2:
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{
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Registers::MemoryFillConfig& config = g_regs.memory_fill[(addr - Registers::MemoryFillValue1) / 0x10];
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config.value = data;
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// TODO: Not sure if this check should be done at GSP level instead
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if (config.address_start) {
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// TODO: Not sure if this algorithm is correct, particularly because it doesn't use the size member at all
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u32* start = (u32*)Memory::GetPointer(config.GetStartAddress());
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u32* end = (u32*)Memory::GetPointer(config.GetEndAddress());
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for (u32* ptr = start; ptr < end; ++ptr)
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*ptr = bswap32(config.value); // TODO: This is just a workaround to missing framebuffer format emulation
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DEBUG_LOG(GPU, "MemoryFill from %x to %x", config.GetStartAddress(), config.GetEndAddress());
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}
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break;
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}
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// TODO: Framebuffer registers!!
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case Registers::FramebufferTopSwapBuffers:
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g_regs.top_framebuffer.active_fb = data;
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@ -240,8 +294,6 @@ inline void Write(u32 addr, const T data) {
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g_regs.display_transfer.output_width * 4);
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}
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// Clear previous contents until we implement proper buffer clearing
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memset(source_pointer, 0x20, g_regs.display_transfer.input_width*g_regs.display_transfer.input_height*4);
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DEBUG_LOG(GPU, "DisplayTriggerTransfer: %x bytes from %x(%xx%x)-> %x(%xx%x), dst format %x",
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g_regs.display_transfer.output_height * g_regs.display_transfer.output_width * 4,
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g_regs.display_transfer.GetPhysicalInputAddress(), (int)g_regs.display_transfer.input_width, (int)g_regs.display_transfer.input_height,
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@ -14,6 +14,15 @@ static const u32 kFrameTicks = kFrameCycles / 3; ///< Approximate number of i
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struct Registers {
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enum Id : u32 {
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MemoryFillStart1 = 0x1EF00010,
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MemoryFillEnd1 = 0x1EF00014,
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MemoryFillSize1 = 0x1EF00018,
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MemoryFillValue1 = 0x1EF0001C,
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MemoryFillStart2 = 0x1EF00020,
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MemoryFillEnd2 = 0x1EF00024,
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MemoryFillSize2 = 0x1EF00028,
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MemoryFillValue2 = 0x1EF0002C,
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FramebufferTopSize = 0x1EF0045C,
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FramebufferTopLeft1 = 0x1EF00468, // Main LCD, first framebuffer for 3D left
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FramebufferTopLeft2 = 0x1EF0046C, // Main LCD, second framebuffer for 3D left
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@ -53,6 +62,23 @@ struct Registers {
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RGBA4 = 4,
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};
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struct MemoryFillConfig {
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u32 address_start;
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u32 address_end; // ?
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u32 size;
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u32 value; // ?
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inline u32 GetStartAddress() const {
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return address_start * 8;
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}
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inline u32 GetEndAddress() const {
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return address_end * 8;
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}
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};
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MemoryFillConfig memory_fill[2];
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// TODO: Move these into the framebuffer struct
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u32 framebuffer_top_left_1;
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u32 framebuffer_top_left_2;
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