Merge pull request #1071 from bunnei/fix-ldc
gl_shader_decompiler: Several fixes for indirect constant buffer loads.
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commit
c8cd1785e6
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@ -383,15 +383,13 @@ public:
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}
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}
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std::string GetUniformIndirect(u64 index, s64 offset, const Register& index_reg,
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std::string GetUniformIndirect(u64 cbuf_index, s64 offset, const std::string& index_str,
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GLSLRegister::Type type) {
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declr_const_buffers[index].MarkAsUsedIndirect(index, stage);
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declr_const_buffers[cbuf_index].MarkAsUsedIndirect(cbuf_index, stage);
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std::string final_offset = "((floatBitsToInt(" + GetRegister(index_reg, 0) + ") + " +
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std::to_string(offset) + ") / 4)";
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std::string value =
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'c' + std::to_string(index) + '[' + final_offset + " / 4][" + final_offset + " % 4]";
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std::string final_offset = fmt::format("({} + {})", index_str, offset / 4);
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std::string value = 'c' + std::to_string(cbuf_index) + '[' + final_offset + " / 4][" +
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final_offset + " % 4]";
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if (type == GLSLRegister::Type::Float) {
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return value;
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@ -1355,11 +1353,16 @@ private:
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case OpCode::Id::LD_C: {
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ASSERT_MSG(instr.ld_c.unknown == 0, "Unimplemented");
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// Add an extra scope and declare the index register inside to prevent
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// overwriting it in case it is used as an output of the LD instruction.
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shader.AddLine("{");
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++shader.scope;
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shader.AddLine("uint index = (" + regs.GetRegisterAsInteger(instr.gpr8, 0, false) +
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" / 4) & (MAX_CONSTBUFFER_ELEMENTS - 1);");
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std::string op_a =
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regs.GetUniformIndirect(instr.cbuf36.index, instr.cbuf36.offset + 0, instr.gpr8,
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GLSLRegister::Type::Float);
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std::string op_b =
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regs.GetUniformIndirect(instr.cbuf36.index, instr.cbuf36.offset + 4, instr.gpr8,
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regs.GetUniformIndirect(instr.cbuf36.index, instr.cbuf36.offset + 0, "index",
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GLSLRegister::Type::Float);
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switch (instr.ld_c.type.Value()) {
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@ -1367,16 +1370,22 @@ private:
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regs.SetRegisterToFloat(instr.gpr0, 0, op_a, 1, 1);
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break;
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case Tegra::Shader::UniformType::Double:
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case Tegra::Shader::UniformType::Double: {
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std::string op_b =
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regs.GetUniformIndirect(instr.cbuf36.index, instr.cbuf36.offset + 4,
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"index", GLSLRegister::Type::Float);
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regs.SetRegisterToFloat(instr.gpr0, 0, op_a, 1, 1);
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regs.SetRegisterToFloat(instr.gpr0.Value() + 1, 0, op_b, 1, 1);
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break;
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}
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default:
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LOG_CRITICAL(HW_GPU, "Unhandled type: {}",
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static_cast<unsigned>(instr.ld_c.type.Value()));
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UNREACHABLE();
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}
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--shader.scope;
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shader.AddLine("}");
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break;
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}
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case OpCode::Id::ST_A: {
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