dyncom: Implement USAT16/SSAT16
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b3240f6455
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@ -2551,7 +2551,22 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(ssat)(unsigned int inst, int index)
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return inst_base;
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(ssat16)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SSAT16"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(ssat16)(unsigned int inst, int index)
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{
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arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ssat_inst));
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ssat_inst* const inst_cream = (ssat_inst*)inst_base->component;
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inst_base->cond = BITS(inst, 28, 31);
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inst_base->idx = index;
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inst_base->br = NON_BRANCH;
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inst_base->load_r15 = 0;
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inst_cream->Rn = BITS(inst, 0, 3);
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inst_cream->Rd = BITS(inst, 12, 15);
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inst_cream->sat_imm = BITS(inst, 16, 19);
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return inst_base;
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(ssub8)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SSUB8"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(ssub16)(unsigned int inst, int index)
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{
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@ -3157,7 +3172,10 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(usat)(unsigned int inst, int index)
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{
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return INTERPRETER_TRANSLATE(ssat)(inst, index);
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(usat16)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("USAT16"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(usat16)(unsigned int inst, int index)
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{
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return INTERPRETER_TRANSLATE(ssat16)(inst, index);
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(usub16)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("USUB16"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(usub8)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("USUB8"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(usubaddx)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("USUBADDX"); }
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@ -5575,6 +5593,26 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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}
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SSAT16_INST:
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{
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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ssat_inst* const inst_cream = (ssat_inst*)inst_base->component;
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const u8 saturate_to = inst_cream->sat_imm;
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bool sat1 = false;
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bool sat2 = false;
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RD = (ARMul_SignedSatQ((s16)RN, saturate_to, &sat1) & 0xFFFF) |
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ARMul_SignedSatQ((s32)RN >> 16, saturate_to, &sat2) << 16;
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if (sat1 || sat2)
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cpu->Cpsr |= (1 << 27);
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}
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cpu->Reg[15] += GET_INST_SIZE(cpu);
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INC_PC(sizeof(ssat_inst));
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FETCH_INST;
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GOTO_NEXT_INST;
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}
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SSUB8_INST:
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STC_INST:
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{
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@ -6355,6 +6393,27 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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}
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USAT16_INST:
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{
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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ssat_inst* const inst_cream = (ssat_inst*)inst_base->component;
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const u8 saturate_to = inst_cream->sat_imm;
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bool sat1 = false;
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bool sat2 = false;
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RD = (ARMul_UnsignedSatQ((s16)RN, saturate_to, &sat1) & 0xFFFF) |
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ARMul_UnsignedSatQ((s32)RN >> 16, saturate_to, &sat2) << 16;
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if (sat1 || sat2)
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cpu->Cpsr |= (1 << 27);
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}
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cpu->Reg[15] += GET_INST_SIZE(cpu);
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INC_PC(sizeof(ssat_inst));
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FETCH_INST;
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GOTO_NEXT_INST;
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}
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USUB16_INST:
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USUB8_INST:
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USUBADDX_INST:
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