Merge pull request #13149 from liamwhite/per-channel-program
video_core: make gpu context aware of rendering program
This commit is contained in:
commit
ce62fa6f7b
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@ -435,8 +435,6 @@ struct Values {
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linkage, false, "disable_shader_loop_safety_checks", Category::RendererDebug};
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Setting<bool> enable_renderdoc_hotkey{linkage, false, "renderdoc_hotkey",
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Category::RendererDebug};
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// TODO: remove this once AMDVLK supports VK_EXT_depth_bias_control
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bool renderer_amdvlk_depth_bias_workaround{};
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Setting<bool> disable_buffer_reorder{linkage, false, "disable_buffer_reorder",
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Category::RendererDebug};
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@ -425,11 +425,6 @@ struct System::Impl {
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room_member->SendGameInfo(game_info);
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}
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// Workarounds:
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// Activate this in Super Smash Brothers Ultimate, it only affects AMD cards using AMDVLK
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Settings::values.renderer_amdvlk_depth_bias_workaround =
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params.program_id == 0x1006A800016E000ULL;
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status = SystemResultStatus::Success;
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return status;
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}
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@ -489,9 +484,6 @@ struct System::Impl {
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room_member->SendGameInfo(game_info);
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}
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// Workarounds
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Settings::values.renderer_amdvlk_depth_bias_workaround = false;
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LOG_DEBUG(Core, "Shutdown OK");
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}
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@ -5,6 +5,7 @@
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#include "common/assert.h"
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#include "common/logging/log.h"
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#include "core/core.h"
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#include "core/hle/kernel/k_process.h"
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#include "core/hle/service/nvdrv/core/container.h"
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#include "core/hle/service/nvdrv/core/nvmap.h"
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#include "core/hle/service/nvdrv/core/syncpoint_manager.h"
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@ -75,7 +76,7 @@ NvResult nvhost_gpu::Ioctl1(DeviceFD fd, Ioctl command, std::span<const u8> inpu
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case 0xd:
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return WrapFixed(this, &nvhost_gpu::SetChannelPriority, input, output);
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case 0x1a:
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return WrapFixed(this, &nvhost_gpu::AllocGPFIFOEx2, input, output);
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return WrapFixed(this, &nvhost_gpu::AllocGPFIFOEx2, input, output, fd);
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case 0x1b:
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return WrapFixedVariable(this, &nvhost_gpu::SubmitGPFIFOBase1, input, output, true);
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case 0x1d:
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@ -120,8 +121,13 @@ NvResult nvhost_gpu::Ioctl3(DeviceFD fd, Ioctl command, std::span<const u8> inpu
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return NvResult::NotImplemented;
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}
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void nvhost_gpu::OnOpen(NvCore::SessionId session_id, DeviceFD fd) {}
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void nvhost_gpu::OnClose(DeviceFD fd) {}
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void nvhost_gpu::OnOpen(NvCore::SessionId session_id, DeviceFD fd) {
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sessions[fd] = session_id;
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}
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void nvhost_gpu::OnClose(DeviceFD fd) {
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sessions.erase(fd);
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}
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NvResult nvhost_gpu::SetNVMAPfd(IoctlSetNvmapFD& params) {
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LOG_DEBUG(Service_NVDRV, "called, fd={}", params.nvmap_fd);
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@ -161,7 +167,7 @@ NvResult nvhost_gpu::SetChannelPriority(IoctlChannelSetPriority& params) {
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return NvResult::Success;
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}
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NvResult nvhost_gpu::AllocGPFIFOEx2(IoctlAllocGpfifoEx2& params) {
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NvResult nvhost_gpu::AllocGPFIFOEx2(IoctlAllocGpfifoEx2& params, DeviceFD fd) {
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LOG_WARNING(Service_NVDRV,
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"(STUBBED) called, num_entries={:X}, flags={:X}, unk0={:X}, "
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"unk1={:X}, unk2={:X}, unk3={:X}",
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@ -173,7 +179,12 @@ NvResult nvhost_gpu::AllocGPFIFOEx2(IoctlAllocGpfifoEx2& params) {
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return NvResult::AlreadyAllocated;
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}
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system.GPU().InitChannel(*channel_state);
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u64 program_id{};
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if (auto* const session = core.GetSession(sessions[fd]); session != nullptr) {
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program_id = session->process->GetProgramId();
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}
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system.GPU().InitChannel(*channel_state, program_id);
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params.fence_out = syncpoint_manager.GetSyncpointFence(channel_syncpoint);
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@ -192,7 +192,7 @@ private:
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NvResult ZCullBind(IoctlZCullBind& params);
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NvResult SetErrorNotifier(IoctlSetErrorNotifier& params);
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NvResult SetChannelPriority(IoctlChannelSetPriority& params);
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NvResult AllocGPFIFOEx2(IoctlAllocGpfifoEx2& params);
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NvResult AllocGPFIFOEx2(IoctlAllocGpfifoEx2& params, DeviceFD fd);
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NvResult AllocateObjectContext(IoctlAllocObjCtx& params);
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NvResult SubmitGPFIFOImpl(IoctlSubmitGpfifo& params, Tegra::CommandList&& entries);
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@ -210,6 +210,7 @@ private:
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NvCore::SyncpointManager& syncpoint_manager;
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NvCore::NvMap& nvmap;
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std::shared_ptr<Tegra::Control::ChannelState> channel_state;
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std::unordered_map<DeviceFD, NvCore::SessionId> sessions;
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u32 channel_syncpoint;
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std::mutex channel_mutex;
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@ -16,8 +16,9 @@ namespace Tegra::Control {
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ChannelState::ChannelState(s32 bind_id_) : bind_id{bind_id_}, initialized{} {}
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void ChannelState::Init(Core::System& system, GPU& gpu) {
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void ChannelState::Init(Core::System& system, GPU& gpu, u64 program_id_) {
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ASSERT(memory_manager);
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program_id = program_id_;
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dma_pusher = std::make_unique<Tegra::DmaPusher>(system, gpu, *memory_manager, *this);
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maxwell_3d = std::make_unique<Engines::Maxwell3D>(system, *memory_manager);
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fermi_2d = std::make_unique<Engines::Fermi2D>(*memory_manager);
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@ -40,11 +40,12 @@ struct ChannelState {
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ChannelState(ChannelState&& other) noexcept = default;
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ChannelState& operator=(ChannelState&& other) noexcept = default;
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void Init(Core::System& system, GPU& gpu);
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void Init(Core::System& system, GPU& gpu, u64 program_id);
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void BindRasterizer(VideoCore::RasterizerInterface* rasterizer);
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s32 bind_id = -1;
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u64 program_id = 0;
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/// 3D engine
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std::unique_ptr<Engines::Maxwell3D> maxwell_3d;
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/// 2D engine
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@ -7,7 +7,7 @@ namespace VideoCommon {
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ChannelInfo::ChannelInfo(Tegra::Control::ChannelState& channel_state)
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: maxwell3d{*channel_state.maxwell_3d}, kepler_compute{*channel_state.kepler_compute},
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gpu_memory{*channel_state.memory_manager} {}
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gpu_memory{*channel_state.memory_manager}, program_id{channel_state.program_id} {}
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template class VideoCommon::ChannelSetupCaches<VideoCommon::ChannelInfo>;
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@ -39,6 +39,7 @@ public:
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Tegra::Engines::Maxwell3D& maxwell3d;
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Tegra::Engines::KeplerCompute& kepler_compute;
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Tegra::MemoryManager& gpu_memory;
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u64 program_id;
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};
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template <class P>
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@ -77,9 +78,10 @@ protected:
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P* channel_state;
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size_t current_channel_id{UNSET_CHANNEL};
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size_t current_address_space{};
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Tegra::Engines::Maxwell3D* maxwell3d;
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Tegra::Engines::KeplerCompute* kepler_compute;
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Tegra::MemoryManager* gpu_memory;
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Tegra::Engines::Maxwell3D* maxwell3d{};
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Tegra::Engines::KeplerCompute* kepler_compute{};
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Tegra::MemoryManager* gpu_memory{};
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u64 program_id{};
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std::deque<P> channel_storage;
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std::deque<size_t> free_channel_ids;
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@ -58,6 +58,7 @@ void ChannelSetupCaches<P>::BindToChannel(s32 id) {
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maxwell3d = &channel_state->maxwell3d;
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kepler_compute = &channel_state->kepler_compute;
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gpu_memory = &channel_state->gpu_memory;
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program_id = channel_state->program_id;
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current_address_space = gpu_memory->GetID();
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}
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@ -76,6 +77,7 @@ void ChannelSetupCaches<P>::EraseChannel(s32 id) {
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maxwell3d = nullptr;
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kepler_compute = nullptr;
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gpu_memory = nullptr;
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program_id = 0;
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} else if (current_channel_id != UNSET_CHANNEL) {
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channel_state = &channel_storage[current_channel_id];
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}
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@ -67,8 +67,8 @@ struct GPU::Impl {
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return CreateChannel(new_channel_id++);
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}
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void InitChannel(Control::ChannelState& to_init) {
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to_init.Init(system, gpu);
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void InitChannel(Control::ChannelState& to_init, u64 program_id) {
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to_init.Init(system, gpu, program_id);
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to_init.BindRasterizer(rasterizer);
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rasterizer->InitializeChannel(to_init);
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}
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@ -412,8 +412,8 @@ std::shared_ptr<Control::ChannelState> GPU::AllocateChannel() {
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return impl->AllocateChannel();
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}
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void GPU::InitChannel(Control::ChannelState& to_init) {
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impl->InitChannel(to_init);
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void GPU::InitChannel(Control::ChannelState& to_init, u64 program_id) {
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impl->InitChannel(to_init, program_id);
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}
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void GPU::BindChannel(s32 channel_id) {
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@ -149,7 +149,7 @@ public:
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std::shared_ptr<Control::ChannelState> AllocateChannel();
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void InitChannel(Control::ChannelState& to_init);
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void InitChannel(Control::ChannelState& to_init, u64 program_id);
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void BindChannel(s32 channel_id);
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@ -1054,37 +1054,16 @@ void RasterizerVulkan::UpdateDepthBias(Tegra::Engines::Maxwell3D::Regs& regs) {
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regs.zeta.format == Tegra::DepthFormat::X8Z24_UNORM ||
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regs.zeta.format == Tegra::DepthFormat::S8Z24_UNORM ||
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regs.zeta.format == Tegra::DepthFormat::V8Z24_UNORM;
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bool force_unorm = ([&] {
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if (!is_d24 || device.SupportsD24DepthBuffer()) {
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return false;
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}
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if (device.IsExtDepthBiasControlSupported()) {
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return true;
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}
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if (!Settings::values.renderer_amdvlk_depth_bias_workaround) {
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return false;
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}
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if (is_d24 && !device.SupportsD24DepthBuffer() && program_id == 0x1006A800016E000ULL) {
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// Only activate this in Super Smash Brothers Ultimate
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// the base formulas can be obtained from here:
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// https://docs.microsoft.com/en-us/windows/win32/direct3d11/d3d10-graphics-programming-guide-output-merger-stage-depth-bias
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const double rescale_factor =
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static_cast<double>(1ULL << (32 - 24)) / (static_cast<double>(0x1.ep+127));
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units = static_cast<float>(static_cast<double>(units) * rescale_factor);
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return false;
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})();
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}
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scheduler.Record([constant = units, clamp = regs.depth_bias_clamp,
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factor = regs.slope_scale_depth_bias, force_unorm,
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precise = device.HasExactDepthBiasControl()](vk::CommandBuffer cmdbuf) {
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if (force_unorm) {
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VkDepthBiasRepresentationInfoEXT info{
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.sType = VK_STRUCTURE_TYPE_DEPTH_BIAS_REPRESENTATION_INFO_EXT,
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.pNext = nullptr,
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.depthBiasRepresentation =
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VK_DEPTH_BIAS_REPRESENTATION_LEAST_REPRESENTABLE_VALUE_FORCE_UNORM_EXT,
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.depthBiasExact = precise ? VK_TRUE : VK_FALSE,
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};
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cmdbuf.SetDepthBias(constant, clamp, factor, &info);
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return;
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}
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factor = regs.slope_scale_depth_bias](vk::CommandBuffer cmdbuf) {
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cmdbuf.SetDepthBias(constant, clamp, factor);
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});
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}
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