gl_rasterizer_cache: Track texture depth.
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@ -51,6 +51,7 @@ static VAddr TryGetCpuAddr(Tegra::GPUVAddr gpu_addr) {
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params.type = GetFormatType(params.pixel_format);
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params.width = Common::AlignUp(config.tic.Width(), GetCompressionFactor(params.pixel_format));
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params.height = Common::AlignUp(config.tic.Height(), GetCompressionFactor(params.pixel_format));
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params.depth = config.tic.Depth();
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params.unaligned_height = config.tic.Height();
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params.size_in_bytes = params.SizeInBytes();
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params.cache_width = Common::AlignUp(params.width, 16);
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@ -70,6 +71,7 @@ static VAddr TryGetCpuAddr(Tegra::GPUVAddr gpu_addr) {
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params.type = GetFormatType(params.pixel_format);
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params.width = config.width;
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params.height = config.height;
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params.depth = 1;
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params.unaligned_height = config.height;
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params.size_in_bytes = params.SizeInBytes();
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params.cache_width = Common::AlignUp(params.width, 16);
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@ -88,9 +90,9 @@ static VAddr TryGetCpuAddr(Tegra::GPUVAddr gpu_addr) {
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params.pixel_format = PixelFormatFromDepthFormat(format);
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params.component_type = ComponentTypeFromDepthFormat(format);
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params.type = GetFormatType(params.pixel_format);
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params.size_in_bytes = params.SizeInBytes();
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params.width = zeta_width;
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params.height = zeta_height;
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params.depth = 1;
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params.unaligned_height = zeta_height;
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params.size_in_bytes = params.SizeInBytes();
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params.cache_width = Common::AlignUp(params.width, 16);
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@ -662,7 +662,7 @@ struct SurfaceParams {
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ASSERT(width % compression_factor == 0);
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ASSERT(height % compression_factor == 0);
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return (width / compression_factor) * (height / compression_factor) *
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GetFormatBpp(pixel_format) / CHAR_BIT;
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GetFormatBpp(pixel_format) * depth / CHAR_BIT;
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}
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/// Creates SurfaceParams from a texture configuration
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@ -691,6 +691,7 @@ struct SurfaceParams {
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SurfaceType type;
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u32 width;
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u32 height;
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u32 depth;
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u32 unaligned_height;
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size_t size_in_bytes;
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SurfaceTarget target;
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@ -170,8 +170,12 @@ struct TICEntry {
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BitField<0, 16, u32> width_minus_1;
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BitField<23, 4, TextureType> texture_type;
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};
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u16 height_minus_1;
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INSERT_PADDING_BYTES(10);
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union {
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BitField<0, 16, u32> height_minus_1;
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BitField<16, 15, u32> depth_minus_1;
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};
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INSERT_PADDING_BYTES(8);
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GPUVAddr Address() const {
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return static_cast<GPUVAddr>((static_cast<GPUVAddr>(address_high) << 32) | address_low);
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@ -192,6 +196,10 @@ struct TICEntry {
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return height_minus_1 + 1;
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}
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u32 Depth() const {
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return depth_minus_1 + 1;
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}
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u32 BlockHeight() const {
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ASSERT(header_version == TICHeaderVersion::BlockLinear ||
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header_version == TICHeaderVersion::BlockLinearColorKey);
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