yuzu-emu
/
yuzu-mainline
Archived
1
0
Fork 0
Code

GPU: Added the TIC registers to the Maxwell3D register structure.

This commit is contained in:
Subv 2018-03-19 00:32:57 -05:00
parent 23a0d2d7b7
commit cff7b29bba
1 changed files with 16 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
src/video_core/engines/maxwell_3d.h
View File

@ -62,7 +62,21 @@ public:
union { union {
struct { struct {
INSERT_PADDING_WORDS(0x582); INSERT_PADDING_WORDS(0x55D);
struct {
u32 tic_address_high;
u32 tic_address_low;
u32 tic_limit;
GPUVAddr TICAddress() const {
return static_cast<GPUVAddr>(
(static_cast<GPUVAddr>(tic_address_high) << 32) | tic_address_low);
}
} tic;
INSERT_PADDING_WORDS(0x22);
struct { struct {
u32 code_address_high; u32 code_address_high;
u32 code_address_low; u32 code_address_low;
@ -264,6 +278,7 @@ private:
static_assert(offsetof(Maxwell3D::Regs, field_name) == position * 4, \ static_assert(offsetof(Maxwell3D::Regs, field_name) == position * 4, \
"Field " #field_name " has invalid position") "Field " #field_name " has invalid position")
ASSERT_REG_POSITION(tic, 0x55D);
ASSERT_REG_POSITION(code_address, 0x582); ASSERT_REG_POSITION(code_address, 0x582);
ASSERT_REG_POSITION(draw, 0x585); ASSERT_REG_POSITION(draw, 0x585);
ASSERT_REG_POSITION(query, 0x6C0); ASSERT_REG_POSITION(query, 0x6C0);