Merge pull request #3502 from namkazt/patch-3
shader_decode: Reimplement BFE instructions
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commit
ddafc99776
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@ -911,14 +911,9 @@ union Instruction {
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} fadd32i;
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union {
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BitField<20, 8, u64> shift_position;
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BitField<28, 8, u64> shift_length;
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BitField<48, 1, u64> negate_b;
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BitField<49, 1, u64> negate_a;
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u64 GetLeftShiftValue() const {
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return 32 - (shift_position + shift_length);
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}
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BitField<40, 1, u64> brev;
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BitField<47, 1, u64> rd_cc;
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BitField<48, 1, u64> is_signed;
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} bfe;
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union {
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@ -17,33 +17,60 @@ u32 ShaderIR::DecodeBfe(NodeBlock& bb, u32 pc) {
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const Instruction instr = {program_code[pc]};
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const auto opcode = OpCode::Decode(instr);
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UNIMPLEMENTED_IF(instr.bfe.negate_b);
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Node op_a = GetRegister(instr.gpr8);
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op_a = GetOperandAbsNegInteger(op_a, false, instr.bfe.negate_a, false);
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Node op_b = [&] {
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switch (opcode->get().GetId()) {
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case OpCode::Id::BFE_R:
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return GetRegister(instr.gpr20);
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case OpCode::Id::BFE_C:
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return GetConstBuffer(instr.cbuf34.index, instr.cbuf34.GetOffset());
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case OpCode::Id::BFE_IMM:
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return Immediate(instr.alu.GetSignedImm20_20());
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default:
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UNREACHABLE();
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return Immediate(0);
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}
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}();
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switch (opcode->get().GetId()) {
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case OpCode::Id::BFE_IMM: {
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UNIMPLEMENTED_IF_MSG(instr.generates_cc,
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"Condition codes generation in BFE is not implemented");
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UNIMPLEMENTED_IF_MSG(instr.bfe.rd_cc, "Condition codes in BFE is not implemented");
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const Node inner_shift_imm = Immediate(static_cast<u32>(instr.bfe.GetLeftShiftValue()));
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const Node outer_shift_imm =
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Immediate(static_cast<u32>(instr.bfe.GetLeftShiftValue() + instr.bfe.shift_position));
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const bool is_signed = instr.bfe.is_signed;
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const Node inner_shift =
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Operation(OperationCode::ILogicalShiftLeft, NO_PRECISE, op_a, inner_shift_imm);
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const Node outer_shift =
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Operation(OperationCode::ILogicalShiftRight, NO_PRECISE, inner_shift, outer_shift_imm);
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SetInternalFlagsFromInteger(bb, outer_shift, instr.generates_cc);
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SetRegister(bb, instr.gpr0, outer_shift);
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break;
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}
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default:
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UNIMPLEMENTED_MSG("Unhandled BFE instruction: {}", opcode->get().GetName());
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// using reverse parallel method in
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// https://graphics.stanford.edu/~seander/bithacks.html#ReverseParallel
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// note for later if possible to implement faster method.
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if (instr.bfe.brev) {
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const auto swap = [&](u32 s, u32 mask) {
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Node v1 =
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SignedOperation(OperationCode::ILogicalShiftRight, is_signed, op_a, Immediate(s));
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if (mask != 0) {
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v1 = SignedOperation(OperationCode::IBitwiseAnd, is_signed, std::move(v1),
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Immediate(mask));
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}
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Node v2 = op_a;
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if (mask != 0) {
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v2 = SignedOperation(OperationCode::IBitwiseAnd, is_signed, std::move(v2),
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Immediate(mask));
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}
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v2 = SignedOperation(OperationCode::ILogicalShiftLeft, is_signed, std::move(v2),
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Immediate(s));
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return SignedOperation(OperationCode::IBitwiseOr, is_signed, std::move(v1),
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std::move(v2));
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};
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op_a = swap(1, 0x55555555U);
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op_a = swap(2, 0x33333333U);
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op_a = swap(4, 0x0F0F0F0FU);
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op_a = swap(8, 0x00FF00FFU);
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op_a = swap(16, 0);
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}
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const auto offset = SignedOperation(OperationCode::IBitfieldExtract, is_signed, op_b,
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Immediate(0), Immediate(8));
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const auto bits = SignedOperation(OperationCode::IBitfieldExtract, is_signed, op_b,
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Immediate(8), Immediate(8));
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auto result = SignedOperation(OperationCode::IBitfieldExtract, is_signed, op_a, offset, bits);
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SetRegister(bb, instr.gpr0, std::move(result));
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return pc;
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}
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@ -68,6 +68,8 @@ OperationCode SignedToUnsignedCode(OperationCode operation_code, bool is_signed)
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return OperationCode::UBitwiseXor;
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case OperationCode::IBitwiseNot:
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return OperationCode::UBitwiseNot;
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case OperationCode::IBitfieldExtract:
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return OperationCode::UBitfieldExtract;
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case OperationCode::IBitfieldInsert:
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return OperationCode::UBitfieldInsert;
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case OperationCode::IBitCount:
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