dyncom: Implement QADD8/QSUB8
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7ad400d5a7
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e412c0fc46
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@ -2419,8 +2419,7 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(pld)(unsigned int inst, int index)
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return inst_base;
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return inst_base;
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}
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(qadd)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("QADD"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(qadd)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("QADD"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(qadd8)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("QADD8"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(qadd8)(unsigned int inst, int index)
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ARM_INST_PTR INTERPRETER_TRANSLATE(qadd16)(unsigned int inst, int index)
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{
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{
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arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst));
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arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst));
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generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component;
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generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component;
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@ -2438,21 +2437,28 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(qadd16)(unsigned int inst, int index)
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return inst_base;
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return inst_base;
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}
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(qadd16)(unsigned int inst, int index)
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{
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return INTERPRETER_TRANSLATE(qadd8)(inst, index);
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(qaddsubx)(unsigned int inst, int index)
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ARM_INST_PTR INTERPRETER_TRANSLATE(qaddsubx)(unsigned int inst, int index)
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{
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{
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return INTERPRETER_TRANSLATE(qadd16)(inst, index);
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return INTERPRETER_TRANSLATE(qadd8)(inst, index);
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}
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(qdadd)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("QDADD"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(qdadd)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("QDADD"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(qdsub)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("QDSUB"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(qdsub)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("QDSUB"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(qsub)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("QSUB"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(qsub)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("QSUB"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(qsub8)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("QSUB8"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(qsub8)(unsigned int inst, int index)
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{
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return INTERPRETER_TRANSLATE(qadd8)(inst, index);
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(qsub16)(unsigned int inst, int index)
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ARM_INST_PTR INTERPRETER_TRANSLATE(qsub16)(unsigned int inst, int index)
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{
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{
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return INTERPRETER_TRANSLATE(qadd16)(inst, index);
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return INTERPRETER_TRANSLATE(qadd8)(inst, index);
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}
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(qsubaddx)(unsigned int inst, int index)
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ARM_INST_PTR INTERPRETER_TRANSLATE(qsubaddx)(unsigned int inst, int index)
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{
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{
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return INTERPRETER_TRANSLATE(qadd16)(inst, index);
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return INTERPRETER_TRANSLATE(qadd8)(inst, index);
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}
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(rev)(unsigned int inst, int index)
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ARM_INST_PTR INTERPRETER_TRANSLATE(rev)(unsigned int inst, int index)
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{
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{
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@ -5777,55 +5783,60 @@ unsigned InterpreterMainLoop(ARMul_State* state)
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GOTO_NEXT_INST;
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GOTO_NEXT_INST;
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}
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}
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QADD_INST:
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QADD_INST:
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QADD8_INST:
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QADD8_INST:
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QADD16_INST:
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QADD16_INST:
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QADDSUBX_INST:
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QADDSUBX_INST:
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QSUB8_INST:
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QSUB16_INST:
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QSUB16_INST:
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QSUBADDX_INST:
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QSUBADDX_INST:
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{
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{
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INC_ICOUNTER;
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INC_ICOUNTER;
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component;
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generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component;
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const s16 rm_lo = (RM & 0xFFFF);
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const u16 rm_lo = (RM & 0xFFFF);
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const s16 rm_hi = ((RM >> 16) & 0xFFFF);
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const u16 rm_hi = ((RM >> 16) & 0xFFFF);
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const s16 rn_lo = (RN & 0xFFFF);
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const u16 rn_lo = (RN & 0xFFFF);
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const s16 rn_hi = ((RN >> 16) & 0xFFFF);
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const u16 rn_hi = ((RN >> 16) & 0xFFFF);
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const u8 op2 = inst_cream->op2;
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const u8 op2 = inst_cream->op2;
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s32 lo_result = 0;
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u16 lo_result = 0;
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s32 hi_result = 0;
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u16 hi_result = 0;
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// QADD16
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// QADD16
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if (op2 == 0x00) {
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if (op2 == 0x00) {
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lo_result = (rn_lo + rm_lo);
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lo_result = ARMul_SignedSaturatedAdd16(rn_lo, rm_lo);
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hi_result = (rn_hi + rm_hi);
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hi_result = ARMul_SignedSaturatedAdd16(rn_hi, rm_hi);
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}
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}
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// QASX
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// QASX
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else if (op2 == 0x01) {
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else if (op2 == 0x01) {
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lo_result = (rn_lo - rm_hi);
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lo_result = ARMul_SignedSaturatedSub16(rn_lo, rm_hi);
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hi_result = (rn_hi + rm_lo);
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hi_result = ARMul_SignedSaturatedAdd16(rn_hi, rm_lo);
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}
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}
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// QSAX
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// QSAX
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else if (op2 == 0x02) {
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else if (op2 == 0x02) {
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lo_result = (rn_lo + rm_hi);
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lo_result = ARMul_SignedSaturatedAdd16(rn_lo, rm_hi);
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hi_result = (rn_hi - rm_lo);
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hi_result = ARMul_SignedSaturatedSub16(rn_hi, rm_lo);
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}
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}
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// QSUB16
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// QSUB16
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else if (op2 == 0x03) {
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else if (op2 == 0x03) {
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lo_result = (rn_lo - rm_lo);
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lo_result = ARMul_SignedSaturatedSub16(rn_lo, rm_lo);
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hi_result = (rn_hi - rm_hi);
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hi_result = ARMul_SignedSaturatedSub16(rn_hi, rm_hi);
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}
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// QADD8
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else if (op2 == 0x04) {
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lo_result = ARMul_SignedSaturatedAdd8(rn_lo & 0xFF, rm_lo & 0xFF) |
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ARMul_SignedSaturatedAdd8(rn_lo >> 8, rm_lo >> 8) << 8;
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hi_result = ARMul_SignedSaturatedAdd8(rn_hi & 0xFF, rm_hi & 0xFF) |
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ARMul_SignedSaturatedAdd8(rn_hi >> 8, rm_hi >> 8) << 8;
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}
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// QSUB8
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else if (op2 == 0x07) {
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lo_result = ARMul_SignedSaturatedSub8(rn_lo & 0xFF, rm_lo & 0xFF) |
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ARMul_SignedSaturatedSub8(rn_lo >> 8, rm_lo >> 8) << 8;
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hi_result = ARMul_SignedSaturatedSub8(rn_hi & 0xFF, rm_hi & 0xFF) |
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ARMul_SignedSaturatedSub8(rn_hi >> 8, rm_hi >> 8) << 8;
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}
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}
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if (lo_result > 0x7FFF)
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lo_result = 0x7FFF;
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else if (lo_result < -0x8000)
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lo_result = -0x8000;
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if (hi_result > 0x7FFF)
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hi_result = 0x7FFF;
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else if (hi_result < -0x8000)
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hi_result = -0x8000;
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RD = (lo_result & 0xFFFF) | ((hi_result & 0xFFFF) << 16);
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RD = (lo_result & 0xFFFF) | ((hi_result & 0xFFFF) << 16);
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}
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}
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@ -5839,7 +5850,6 @@ unsigned InterpreterMainLoop(ARMul_State* state)
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QDADD_INST:
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QDADD_INST:
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QDSUB_INST:
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QDSUB_INST:
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QSUB_INST:
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QSUB_INST:
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QSUB8_INST:
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REV_INST:
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REV_INST:
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{
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{
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INC_ICOUNTER;
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INC_ICOUNTER;
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