Vulkan Implement Dynamic State 2 LogicOp and PatchVertices
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c897c55e3c
commit
f800e485c9
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@ -124,6 +124,7 @@ void Maxwell3D::InitializeRegisterDefaults() {
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regs.gl_front_face = Maxwell3D::Regs::FrontFace::ClockWise;
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regs.polygon_mode_back = Maxwell3D::Regs::PolygonMode::Fill;
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regs.polygon_mode_front = Maxwell3D::Regs::PolygonMode::Fill;
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regs.logic_op.op = Maxwell3D::Regs::LogicOp::Op::Clear;
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shadow_state = regs;
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}
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@ -55,6 +55,7 @@ void FixedPipelineState::Refresh(Tegra::Engines::Maxwell3D& maxwell3d, DynamicFe
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raw1 = 0;
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extended_dynamic_state.Assign(features.has_extended_dynamic_state ? 1 : 0);
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extended_dynamic_state_2.Assign(features.has_extended_dynamic_state_2 ? 1 : 0);
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extended_dynamic_state_2_extra.Assign(features.has_extended_dynamic_state_2_extra ? 1 : 0);
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extended_dynamic_state_3.Assign(features.has_extended_dynamic_state_3 ? 1 : 0);
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dynamic_vertex_input.Assign(features.has_dynamic_vertex_input ? 1 : 0);
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xfb_enabled.Assign(regs.transform_feedback_enabled != 0);
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@ -66,13 +67,12 @@ void FixedPipelineState::Refresh(Tegra::Engines::Maxwell3D& maxwell3d, DynamicFe
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Maxwell::ViewportClipControl::GeometryClip::FrustumZ);
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ndc_minus_one_to_one.Assign(regs.depth_mode == Maxwell::DepthMode::MinusOneToOne ? 1 : 0);
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polygon_mode.Assign(PackPolygonMode(regs.polygon_mode_front));
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patch_control_points_minus_one.Assign(regs.patch_vertices - 1);
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tessellation_primitive.Assign(static_cast<u32>(regs.tessellation.params.domain_type.Value()));
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tessellation_spacing.Assign(static_cast<u32>(regs.tessellation.params.spacing.Value()));
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tessellation_clockwise.Assign(regs.tessellation.params.output_primitives.Value() ==
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Maxwell::Tessellation::OutputPrimitives::Triangles_CW);
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logic_op_enable.Assign(regs.logic_op.enable != 0 ? 1 : 0);
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logic_op.Assign(PackLogicOp(regs.logic_op.op));
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patch_control_points_minus_one.Assign(regs.patch_vertices - 1);
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topology.Assign(topology_);
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msaa_mode.Assign(regs.anti_alias_samples_mode);
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@ -156,8 +156,8 @@ void FixedPipelineState::Refresh(Tegra::Engines::Maxwell3D& maxwell3d, DynamicFe
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if (!extended_dynamic_state) {
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dynamic_state.Refresh(regs);
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}
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if (!extended_dynamic_state_2) {
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dynamic_state.Refresh2(regs, topology);
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if (!extended_dynamic_state_2_extra) {
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dynamic_state.Refresh2(regs, topology, extended_dynamic_state_2);
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}
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if (!extended_dynamic_state_3) {
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dynamic_state.Refresh3(regs);
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@ -241,7 +241,13 @@ void FixedPipelineState::DynamicState::Refresh(const Maxwell& regs) {
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});
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}
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void FixedPipelineState::DynamicState::Refresh2(const Maxwell& regs, Maxwell::PrimitiveTopology topology_) {
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void FixedPipelineState::DynamicState::Refresh2(const Maxwell& regs, Maxwell::PrimitiveTopology topology_, bool base_feautures_supported) {
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logic_op.Assign(PackLogicOp(regs.logic_op.op));
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if (base_feautures_supported) {
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return;
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}
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const std::array enabled_lut{
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regs.polygon_offset_point_enable,
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regs.polygon_offset_line_enable,
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@ -146,6 +146,7 @@ struct FixedPipelineState {
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BitField<3, 1, u32> primitive_restart_enable;
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BitField<4, 1, u32> depth_bias_enable;
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BitField<5, 1, u32> rasterize_enable;
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BitField<6, 4, u32> logic_op;
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};
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union {
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u32 raw2;
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@ -162,7 +163,7 @@ struct FixedPipelineState {
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std::array<u16, Maxwell::NumVertexArrays> vertex_strides;
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void Refresh(const Maxwell& regs);
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void Refresh2(const Maxwell& regs, Maxwell::PrimitiveTopology topology);
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void Refresh2(const Maxwell& regs, Maxwell::PrimitiveTopology topology, bool base_feautures_supported);
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void Refresh3(const Maxwell& regs);
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Maxwell::ComparisonOp DepthTestFunc() const noexcept {
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@ -182,18 +183,19 @@ struct FixedPipelineState {
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u32 raw1;
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BitField<0, 1, u32> extended_dynamic_state;
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BitField<1, 1, u32> extended_dynamic_state_2;
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BitField<2, 1, u32> extended_dynamic_state_3;
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BitField<3, 1, u32> dynamic_vertex_input;
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BitField<4, 1, u32> xfb_enabled;
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BitField<5, 1, u32> depth_clamp_disabled;
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BitField<6, 1, u32> ndc_minus_one_to_one;
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BitField<7, 2, u32> polygon_mode;
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BitField<9, 5, u32> patch_control_points_minus_one;
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BitField<14, 2, u32> tessellation_primitive;
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BitField<16, 2, u32> tessellation_spacing;
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BitField<18, 1, u32> tessellation_clockwise;
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BitField<19, 1, u32> logic_op_enable;
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BitField<20, 4, u32> logic_op;
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BitField<2, 1, u32> extended_dynamic_state_2_extra;
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BitField<3, 1, u32> extended_dynamic_state_3;
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BitField<4, 1, u32> dynamic_vertex_input;
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BitField<5, 1, u32> xfb_enabled;
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BitField<6, 1, u32> depth_clamp_disabled;
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BitField<7, 1, u32> ndc_minus_one_to_one;
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BitField<8, 2, u32> polygon_mode;
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BitField<10, 2, u32> tessellation_primitive;
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BitField<12, 2, u32> tessellation_spacing;
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BitField<14, 1, u32> tessellation_clockwise;
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BitField<15, 1, u32> logic_op_enable;
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BitField<16, 5, u32> patch_control_points_minus_one;
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BitField<24, 4, Maxwell::PrimitiveTopology> topology;
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BitField<28, 4, Tegra::Texture::MsaaMode> msaa_mode;
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};
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@ -246,7 +248,7 @@ struct FixedPipelineState {
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// Exclude dynamic state and attributes
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return offsetof(FixedPipelineState, attributes);
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}
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if (extended_dynamic_state_2) {
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if (extended_dynamic_state_2_extra) {
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// Exclude dynamic state
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return offsetof(FixedPipelineState, dynamic_state);
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}
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@ -628,7 +628,7 @@ void GraphicsPipeline::MakePipeline(VkRenderPass render_pass) {
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.pNext = nullptr,
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.flags = 0,
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.topology = input_assembly_topology,
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.primitiveRestartEnable = key.state.dynamic_state.primitive_restart_enable != 0 &&
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.primitiveRestartEnable = dynamic.primitive_restart_enable != 0 &&
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((input_assembly_topology != VK_PRIMITIVE_TOPOLOGY_PATCH_LIST &&
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device.IsTopologyListPrimitiveRestartSupported()) ||
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SupportsPrimitiveRestart(input_assembly_topology) ||
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@ -786,12 +786,12 @@ void GraphicsPipeline::MakePipeline(VkRenderPass render_pass) {
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.pNext = nullptr,
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.flags = 0,
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.logicOpEnable = key.state.logic_op_enable != 0,
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.logicOp = static_cast<VkLogicOp>(key.state.logic_op.Value()),
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.logicOp = static_cast<VkLogicOp>(dynamic.logic_op.Value()),
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.attachmentCount = static_cast<u32>(cb_attachments.size()),
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.pAttachments = cb_attachments.data(),
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.blendConstants = {},
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};
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static_vector<VkDynamicState, 22> dynamic_states{
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static_vector<VkDynamicState, 23> dynamic_states{
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VK_DYNAMIC_STATE_VIEWPORT, VK_DYNAMIC_STATE_SCISSOR,
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VK_DYNAMIC_STATE_DEPTH_BIAS, VK_DYNAMIC_STATE_BLEND_CONSTANTS,
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VK_DYNAMIC_STATE_DEPTH_BOUNDS, VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
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@ -822,6 +822,9 @@ void GraphicsPipeline::MakePipeline(VkRenderPass render_pass) {
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};
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dynamic_states.insert(dynamic_states.end(), extended2.begin(), extended2.end());
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}
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if (key.state.extended_dynamic_state_2_extra) {
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dynamic_states.push_back(VK_DYNAMIC_STATE_LOGIC_OP_EXT);
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}
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}
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const VkPipelineDynamicStateCreateInfo dynamic_state_ci{
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.sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
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@ -454,6 +454,8 @@ void PipelineCache::LoadDiskResources(u64 title_id, std::stop_token stop_loading
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dynamic_features.has_extended_dynamic_state ||
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(key.state.extended_dynamic_state_2 != 0) !=
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dynamic_features.has_extended_dynamic_state_2 ||
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(key.state.extended_dynamic_state_2_extra != 0) !=
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dynamic_features.has_extended_dynamic_state_2_extra ||
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(key.state.extended_dynamic_state_3 != 0) !=
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dynamic_features.has_extended_dynamic_state_3 ||
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(key.state.dynamic_vertex_input != 0) != dynamic_features.has_dynamic_vertex_input) {
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@ -680,7 +680,6 @@ void RasterizerVulkan::UpdateDynamicStates() {
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UpdateLineWidth(regs);
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if (device.IsExtExtendedDynamicStateSupported()) {
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UpdateCullMode(regs);
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UpdateDepthCompareOp(regs);
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UpdateFrontFace(regs);
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UpdateStencilOp(regs);
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@ -700,6 +699,9 @@ void RasterizerVulkan::UpdateDynamicStates() {
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UpdateDepthBiasEnable(regs);
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}
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}
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if (device.IsExtExtendedDynamicState2ExtrasSupported()) {
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UpdateLogicOp(regs);
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}
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}
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}
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@ -1028,6 +1030,17 @@ void RasterizerVulkan::UpdateStencilOp(Tegra::Engines::Maxwell3D::Regs& regs) {
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}
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}
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void RasterizerVulkan::UpdateLogicOp(Tegra::Engines::Maxwell3D::Regs& regs) {
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if (!regs.logic_op.enable) {
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return;
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}
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if (!state_tracker.TouchLogicOp()) {
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return;
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}
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auto op = static_cast<VkLogicOp>(static_cast<u32>(regs.logic_op.op) - 0x1500);
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scheduler.Record([op](vk::CommandBuffer cmdbuf) { cmdbuf.SetLogicOpEXT(op); });
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}
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void RasterizerVulkan::UpdateStencilTestEnable(Tegra::Engines::Maxwell3D::Regs& regs) {
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if (!state_tracker.TouchStencilTestEnable()) {
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return;
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@ -145,6 +145,7 @@ private:
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void UpdateFrontFace(Tegra::Engines::Maxwell3D::Regs& regs);
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void UpdateStencilOp(Tegra::Engines::Maxwell3D::Regs& regs);
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void UpdateStencilTestEnable(Tegra::Engines::Maxwell3D::Regs& regs);
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void UpdateLogicOp(Tegra::Engines::Maxwell3D::Regs& regs);
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void UpdateVertexInput(Tegra::Engines::Maxwell3D::Regs& regs);
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@ -48,6 +48,7 @@ Flags MakeInvalidationFlags() {
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PrimitiveRestartEnable,
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RasterizerDiscardEnable,
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DepthBiasEnable,
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LogicOp,
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};
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Flags flags{};
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for (const int flag : INVALIDATION_FLAGS) {
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@ -162,6 +163,10 @@ void SetupDirtyBlending(Tables& tables) {
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FillBlock(tables[0], OFF(blend_per_target), NUM(blend_per_target), Blending);
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}
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void SetupDirtySpecialOps(Tables& tables) {
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tables[0][OFF(logic_op.op)] = LogicOp;
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}
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void SetupDirtyViewportSwizzles(Tables& tables) {
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static constexpr size_t swizzle_offset = 6;
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for (size_t index = 0; index < Regs::NumViewports; ++index) {
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@ -210,6 +215,7 @@ void StateTracker::SetupTables(Tegra::Control::ChannelState& channel_state) {
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SetupDirtyViewportSwizzles(tables);
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SetupDirtyVertexAttributes(tables);
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SetupDirtyVertexBindings(tables);
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SetupDirtySpecialOps(tables);
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}
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void StateTracker::ChangeChannel(Tegra::Control::ChannelState& channel_state) {
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@ -49,6 +49,7 @@ enum : u8 {
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RasterizerDiscardEnable,
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DepthBiasEnable,
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StateEnable,
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LogicOp,
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Blending,
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ViewportSwizzles,
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@ -159,6 +160,10 @@ public:
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return Exchange(Dirty::StencilTestEnable, false);
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}
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bool TouchLogicOp() {
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return Exchange(Dirty::LogicOp, false);
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}
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bool ChangePrimitiveTopology(Maxwell::PrimitiveTopology new_topology) {
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const bool has_changed = current_topology != new_topology;
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current_topology = new_topology;
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@ -576,8 +576,6 @@ Device::Device(VkInstance instance_, vk::PhysicalDevice physical_, VkSurfaceKHR
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.pNext = nullptr,
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.extendedDynamicState2 = VK_TRUE,
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.extendedDynamicState2LogicOp = ext_extended_dynamic_state2_extra ? VK_TRUE : VK_FALSE,
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.extendedDynamicState2PatchControlPoints =
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ext_extended_dynamic_state2_extra ? VK_TRUE : VK_FALSE,
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};
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SetNext(next, dynamic_state2);
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} else {
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@ -1330,8 +1328,7 @@ std::vector<const char*> Device::LoadExtensions(bool requires_surface) {
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extensions.push_back(VK_EXT_EXTENDED_DYNAMIC_STATE_2_EXTENSION_NAME);
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ext_extended_dynamic_state2 = true;
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ext_extended_dynamic_state2_extra =
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extended_dynamic_state2.extendedDynamicState2LogicOp &&
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extended_dynamic_state2.extendedDynamicState2PatchControlPoints;
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extended_dynamic_state2.extendedDynamicState2LogicOp;
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}
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}
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if (has_ext_extended_dynamic_state3) {
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@ -126,6 +126,8 @@ void Load(VkDevice device, DeviceDispatch& dld) noexcept {
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X(vkCmdSetRasterizerDiscardEnableEXT);
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X(vkCmdSetDepthBiasEnableEXT);
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X(vkCmdSetFrontFaceEXT);
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X(vkCmdSetLogicOpEXT);
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X(vkCmdSetPatchControlPointsEXT);
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X(vkCmdSetLineWidth);
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X(vkCmdSetPrimitiveTopologyEXT);
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X(vkCmdSetStencilOpEXT);
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@ -239,6 +239,8 @@ struct DeviceDispatch : InstanceDispatch {
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PFN_vkCmdSetDepthBiasEnableEXT vkCmdSetDepthBiasEnableEXT{};
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PFN_vkCmdSetEvent vkCmdSetEvent{};
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PFN_vkCmdSetFrontFaceEXT vkCmdSetFrontFaceEXT{};
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PFN_vkCmdSetPatchControlPointsEXT vkCmdSetPatchControlPointsEXT{};
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PFN_vkCmdSetLogicOpEXT vkCmdSetLogicOpEXT{};
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PFN_vkCmdSetLineWidth vkCmdSetLineWidth{};
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PFN_vkCmdSetPrimitiveTopologyEXT vkCmdSetPrimitiveTopologyEXT{};
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PFN_vkCmdSetScissor vkCmdSetScissor{};
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@ -1238,6 +1240,14 @@ public:
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dld->vkCmdSetFrontFaceEXT(handle, front_face);
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}
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void SetLogicOpEXT(VkLogicOp logic_op) const noexcept {
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dld->vkCmdSetLogicOpEXT(handle, logic_op);
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}
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void SetPatchControlPointsEXT(uint32_t patch_control_points) const noexcept {
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dld->vkCmdSetPatchControlPointsEXT(handle, patch_control_points);
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}
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void SetLineWidth(float line_width) const noexcept {
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dld->vkCmdSetLineWidth(handle, line_width);
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}
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