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video_core: Enable ImageGather with subpixel offset on Intel

This commit is contained in:
Wollnashorn 2023-04-05 03:02:24 +02:00
parent 780240e697
commit fe91066f46
7 changed files with 11 additions and 17 deletions

View File

@ -52,9 +52,9 @@ struct Profile {
bool need_declared_frag_colors{};
/// Prevents fast math optimizations that may cause inaccuracies
bool need_fastmath_off{};
/// Some GPU vendors use a lower fixed point format of 16.8 when calculating pixel coordinates
/// in the ImageGather instruction than the Maxwell architecture does. Applying an offset does
/// fix this mismatching rounding behaviour.
/// Some GPU vendors use a different rounding precision when calculating texture pixel
/// coordinates with the 16.8 format in the ImageGather instruction than the Maxwell
/// architecture. Applying an offset does fix this mismatching rounding behaviour.
bool need_gather_subpixel_offset{};
/// OpFClamp is broken and OpFMax + OpFMin should be used instead

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@ -169,7 +169,6 @@ Device::Device(Core::Frontend::EmuWindow& emu_window) {
has_draw_texture = GLAD_GL_NV_draw_texture;
warp_size_potentially_larger_than_guest = !is_nvidia && !is_intel;
need_fastmath_off = is_nvidia;
need_gather_subpixel_offset = is_amd;
can_report_memory = GLAD_GL_NVX_gpu_memory_info;
// At the moment of writing this, only Nvidia's driver optimizes BufferSubData on exclusive

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@ -160,10 +160,6 @@ public:
return need_fastmath_off;
}
bool NeedsGatherSubpixelOffset() const {
return need_gather_subpixel_offset;
}
bool HasCbufFtouBug() const {
return has_cbuf_ftou_bug;
}
@ -180,6 +176,10 @@ public:
return vendor_name == "ATI Technologies Inc.";
}
bool IsIntel() const {
return vendor_name == "Intel";
}
bool CanReportMemoryUsage() const {
return can_report_memory;
}
@ -229,7 +229,6 @@ private:
bool has_draw_texture{};
bool warp_size_potentially_larger_than_guest{};
bool need_fastmath_off{};
bool need_gather_subpixel_offset{};
bool has_cbuf_ftou_bug{};
bool has_bool_ref_bug{};
bool can_report_memory{};

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@ -218,7 +218,7 @@ ShaderCache::ShaderCache(RasterizerOpenGL& rasterizer_, Core::Frontend::EmuWindo
.lower_left_origin_mode = true,
.need_declared_frag_colors = true,
.need_fastmath_off = device.NeedsFastmathOff(),
.need_gather_subpixel_offset = device.NeedsGatherSubpixelOffset(),
.need_gather_subpixel_offset = device.IsAmd() || device.IsIntel(),
.has_broken_spirv_clamp = true,
.has_broken_unsigned_image_offsets = true,

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@ -329,7 +329,9 @@ PipelineCache::PipelineCache(RasterizerVulkan& rasterizer_, const Device& device
.lower_left_origin_mode = false,
.need_declared_frag_colors = false,
.need_gather_subpixel_offset = device.NeedsGatherSubpixelOffset(),
.need_gather_subpixel_offset = driver_id == VK_DRIVER_ID_AMD_PROPRIETARY ||
driver_id == VK_DRIVER_ID_INTEL_PROPRIETARY_WINDOWS ||
driver_id == VK_DRIVER_ID_INTEL_OPEN_SOURCE_MESA,
.has_broken_spirv_clamp = driver_id == VK_DRIVER_ID_INTEL_PROPRIETARY_WINDOWS,
.has_broken_spirv_position_input = driver_id == VK_DRIVER_ID_QUALCOMM_PROPRIETARY,

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@ -431,7 +431,6 @@ Device::Device(VkInstance instance_, vk::PhysicalDevice physical_, VkSurfaceKHR
"AMD GCN4 and earlier have broken VK_IMAGE_CREATE_CUBE_COMPATIBLE_BIT");
has_broken_cube_compatibility = true;
}
need_gather_subpixel_offset = true;
}
if (extensions.sampler_filter_minmax && is_amd) {
// Disable ext_sampler_filter_minmax on AMD GCN4 and lower as it is broken.

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@ -554,10 +554,6 @@ public:
return features.robustness2.nullDescriptor;
}
bool NeedsGatherSubpixelOffset() const {
return need_gather_subpixel_offset;
}
u32 GetMaxVertexInputAttributes() const {
return properties.properties.limits.maxVertexInputAttributes;
}
@ -668,7 +664,6 @@ private:
bool must_emulate_bgr565{}; ///< Emulates BGR565 by swizzling RGB565 format.
bool dynamic_state3_blending{}; ///< Has all blending features of dynamic_state3.
bool dynamic_state3_enables{}; ///< Has all enables features of dynamic_state3.
bool need_gather_subpixel_offset{}; ///< Needs offset at ImageGather for correct rounding.
u64 device_access_memory{}; ///< Total size of device local memory in bytes.
u32 sets_per_pool{}; ///< Sets per Description Pool