dyncom: Move SEL over
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770b274c86
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245276c9cc
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@ -2525,7 +2525,24 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(sbc)(unsigned int inst, int index)
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}
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return inst_base;
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(sel)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SEL"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(sel)(unsigned int inst, int index)
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{
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arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst));
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generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component;
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inst_base->cond = BITS(inst, 28, 31);
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inst_base->idx = index;
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inst_base->br = NON_BRANCH;
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inst_base->load_r15 = 0;
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inst_cream->Rm = BITS(inst, 0, 3);
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inst_cream->Rn = BITS(inst, 16, 19);
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inst_cream->Rd = BITS(inst, 12, 15);
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inst_cream->op1 = BITS(inst, 20, 22);
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inst_cream->op2 = BITS(inst, 5, 7);
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return inst_base;
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(setend)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SETEND"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(shadd16)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SHADD16"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(shadd8)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SHADD8"); }
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@ -5764,7 +5781,47 @@ unsigned InterpreterMainLoop(ARMul_State* state)
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FETCH_INST;
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GOTO_NEXT_INST;
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}
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SEL_INST:
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{
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INC_ICOUNTER;
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component;
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const u32 to = RM;
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const u32 from = RN;
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const u32 cpsr = cpu->Cpsr;
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u32 result;
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if (cpsr & (1 << 16))
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result = from & 0xff;
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else
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result = to & 0xff;
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if (cpsr & (1 << 17))
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result |= from & 0x0000ff00;
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else
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result |= to & 0x0000ff00;
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if (cpsr & (1 << 18))
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result |= from & 0x00ff0000;
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else
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result |= to & 0x00ff0000;
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if (cpsr & (1 << 19))
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result |= from & 0xff000000;
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else
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result |= to & 0xff000000;
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RD = result;
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}
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cpu->Reg[15] += GET_INST_SIZE(cpu);
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INC_PC(sizeof(generic_arm_inst));
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FETCH_INST;
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GOTO_NEXT_INST;
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}
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SETEND_INST:
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SHADD16_INST:
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SHADD8_INST:
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