Merge pull request #4713 from behunin/int-flags
Start of Integer flags implementation
This commit is contained in:
commit
302a5f00e8
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@ -465,6 +465,14 @@ public:
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return operands.size();
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return operands.size();
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}
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}
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NodeBlock& GetOperands() {
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return operands;
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}
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const NodeBlock& GetOperands() const {
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return operands;
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}
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[[nodiscard]] const Node& operator[](std::size_t operand_index) const {
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[[nodiscard]] const Node& operator[](std::size_t operand_index) const {
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return operands.at(operand_index);
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return operands.at(operand_index);
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}
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}
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@ -388,9 +388,54 @@ void ShaderIR::SetInternalFlagsFromInteger(NodeBlock& bb, Node value, bool sets_
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if (!sets_cc) {
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if (!sets_cc) {
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return;
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return;
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}
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}
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Node zerop = Operation(OperationCode::LogicalIEqual, std::move(value), Immediate(0));
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switch (value->index()) {
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SetInternalFlag(bb, InternalFlag::Zero, std::move(zerop));
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case 0: // Operation Node
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LOG_WARNING(HW_GPU, "Condition codes implementation is incomplete");
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SearchOperands(bb, value);
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break;
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case 2: // Genral Purpose Node
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if (const auto* gpr = std::get_if<GprNode>(value.get())) {
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LOG_DEBUG(HW_GPU, "GprNode: index={}", gpr->GetIndex());
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Node zerop = Operation(OperationCode::LogicalIEqual, std::move(value),
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Immediate(gpr->GetIndex()));
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SetInternalFlag(bb, InternalFlag::Zero, std::move(zerop));
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}
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break;
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default:
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Node zerop = Operation(OperationCode::LogicalIEqual, std::move(value), Immediate(0));
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SetInternalFlag(bb, InternalFlag::Zero, std::move(zerop));
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LOG_WARNING(HW_GPU, "Node Type: {}", value->index());
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break;
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}
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}
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void ShaderIR::SearchOperands(NodeBlock& nb, Node var) {
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const auto* op = std::get_if<OperationNode>(var.get());
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if (op == nullptr) {
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return;
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}
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if (op->GetOperandsCount() == 0) {
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return;
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}
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for (auto& operand : op->GetOperands()) {
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switch (operand->index()) {
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case 0: // Operation Node
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return SearchOperands(nb, operand);
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case 2: // General Purpose Node
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if (const auto* gpr = std::get_if<GprNode>(operand.get())) {
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LOG_DEBUG(HW_GPU, "Child GprNode: index={}", gpr->GetIndex());
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Node zerop = Operation(OperationCode::LogicalIEqual, std::move(operand),
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Immediate(gpr->GetIndex()));
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SetInternalFlag(nb, InternalFlag::Zero, std::move(zerop));
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}
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break;
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default:
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LOG_WARNING(HW_GPU, "Child Node Type: {}", operand->index());
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break;
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}
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}
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}
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}
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Node ShaderIR::BitfieldExtract(Node value, u32 offset, u32 bits) {
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Node ShaderIR::BitfieldExtract(Node value, u32 offset, u32 bits) {
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@ -346,6 +346,9 @@ private:
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/// Access a bindless image sampler.
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/// Access a bindless image sampler.
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ImageEntry& GetBindlessImage(Tegra::Shader::Register reg, Tegra::Shader::ImageType type);
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ImageEntry& GetBindlessImage(Tegra::Shader::Register reg, Tegra::Shader::ImageType type);
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/// Recursive Iteration over the OperationNode operands, searching for GprNodes.
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void SearchOperands(NodeBlock& nb, Node var);
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/// Extracts a sequence of bits from a node
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/// Extracts a sequence of bits from a node
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Node BitfieldExtract(Node value, u32 offset, u32 bits);
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Node BitfieldExtract(Node value, u32 offset, u32 bits);
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