Shader JIT: Fix CMP NaN behavior to match hardware
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@ -578,27 +578,42 @@ void JitCompiler::Compile_CALLU(Instruction instr) {
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void JitCompiler::Compile_CMP(Instruction instr) {
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void JitCompiler::Compile_CMP(Instruction instr) {
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using Op = Instruction::Common::CompareOpType::Op;
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Op op_x = instr.common.compare_op.x;
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Op op_y = instr.common.compare_op.y;
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Compile_SwizzleSrc(instr, 1, instr.common.src1, SRC1);
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Compile_SwizzleSrc(instr, 1, instr.common.src1, SRC1);
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Compile_SwizzleSrc(instr, 2, instr.common.src2, SRC2);
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Compile_SwizzleSrc(instr, 2, instr.common.src2, SRC2);
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static const u8 cmp[] = { CMP_EQ, CMP_NEQ, CMP_LT, CMP_LE, CMP_NLE, CMP_NLT };
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// SSE doesn't have greater-than (GT) or greater-equal (GE) comparison operators. You need to
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// emulate them by swapping the lhs and rhs and using LT and LE. NLT and NLE can't be used here
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// because they don't match when used with NaNs.
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static const u8 cmp[] = { CMP_EQ, CMP_NEQ, CMP_LT, CMP_LE, CMP_LT, CMP_LE };
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if (instr.common.compare_op.x == instr.common.compare_op.y) {
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bool invert_op_x = (op_x == Op::GreaterThan || op_x == Op::GreaterEqual);
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Gen::X64Reg lhs_x = invert_op_x ? SRC2 : SRC1;
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Gen::X64Reg rhs_x = invert_op_x ? SRC1 : SRC2;
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if (op_x == op_y) {
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// Compare X-component and Y-component together
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// Compare X-component and Y-component together
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CMPPS(SRC1, R(SRC2), cmp[instr.common.compare_op.x]);
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CMPPS(lhs_x, R(rhs_x), cmp[op_x]);
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MOVQ_xmm(R(COND0), lhs_x);
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MOVQ_xmm(R(COND0), SRC1);
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MOV(64, R(COND1), R(COND0));
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MOV(64, R(COND1), R(COND0));
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} else {
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} else {
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bool invert_op_y = (op_y == Op::GreaterThan || op_y == Op::GreaterEqual);
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Gen::X64Reg lhs_y = invert_op_y ? SRC2 : SRC1;
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Gen::X64Reg rhs_y = invert_op_y ? SRC1 : SRC2;
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// Compare X-component
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// Compare X-component
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MOVAPS(SCRATCH, R(SRC1));
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MOVAPS(SCRATCH, R(lhs_x));
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CMPSS(SCRATCH, R(SRC2), cmp[instr.common.compare_op.x]);
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CMPSS(SCRATCH, R(rhs_x), cmp[op_x]);
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// Compare Y-component
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// Compare Y-component
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CMPPS(SRC1, R(SRC2), cmp[instr.common.compare_op.y]);
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CMPPS(lhs_y, R(rhs_y), cmp[op_y]);
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MOVQ_xmm(R(COND0), SCRATCH);
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MOVQ_xmm(R(COND0), SCRATCH);
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MOVQ_xmm(R(COND1), SRC1);
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MOVQ_xmm(R(COND1), lhs_y);
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}
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}
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SHR(32, R(COND0), Imm8(31));
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SHR(32, R(COND0), Imm8(31));
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