Merge pull request #3024 from lioncash/shadow
video_core/shader: Resolve instances of variable shadowing
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commit
5328d570df
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@ -144,7 +144,7 @@ u32 ShaderIR::DecodeArithmeticInteger(NodeBlock& bb, u32 pc) {
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case OpCode::Id::ICMP_IMM: {
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const Node zero = Immediate(0);
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const auto [op_b, test] = [&]() -> std::pair<Node, Node> {
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const auto [op_rhs, test] = [&]() -> std::pair<Node, Node> {
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switch (opcode->get().GetId()) {
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case OpCode::Id::ICMP_CR:
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return {GetConstBuffer(instr.cbuf34.index, instr.cbuf34.offset),
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@ -161,10 +161,10 @@ u32 ShaderIR::DecodeArithmeticInteger(NodeBlock& bb, u32 pc) {
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return {zero, zero};
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}
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}();
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const Node op_a = GetRegister(instr.gpr8);
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const Node op_lhs = GetRegister(instr.gpr8);
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const Node comparison =
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GetPredicateComparisonInteger(instr.icmp.cond, instr.icmp.is_signed != 0, test, zero);
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SetRegister(bb, instr.gpr0, Operation(OperationCode::Select, comparison, op_a, op_b));
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SetRegister(bb, instr.gpr0, Operation(OperationCode::Select, comparison, op_lhs, op_rhs));
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break;
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}
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case OpCode::Id::LOP_C:
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@ -144,8 +144,8 @@ u32 ShaderIR::DecodeImage(NodeBlock& bb, u32 pc) {
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Image& ShaderIR::GetImage(Tegra::Shader::Image image, Tegra::Shader::ImageType type) {
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const auto offset{static_cast<std::size_t>(image.index.Value())};
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if (const auto image = TryUseExistingImage(offset, type)) {
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return *image;
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if (const auto existing_image = TryUseExistingImage(offset, type)) {
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return *existing_image;
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}
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const std::size_t next_index{used_images.size()};
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@ -67,7 +67,7 @@ u32 ShaderIR::DecodeOther(NodeBlock& bb, u32 pc) {
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break;
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}
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case OpCode::Id::MOV_SYS: {
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const Node value = [&]() {
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const Node value = [this, instr] {
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switch (instr.sys20) {
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case SystemVariable::Ydirection:
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return Operation(OperationCode::YNegate);
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@ -18,7 +18,7 @@ u32 ShaderIR::DecodeShift(NodeBlock& bb, u32 pc) {
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const auto opcode = OpCode::Decode(instr);
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Node op_a = GetRegister(instr.gpr8);
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Node op_b = [&]() {
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Node op_b = [this, instr] {
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if (instr.is_b_imm) {
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return Immediate(instr.alu.GetSignedImm20_20());
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} else if (instr.is_b_gpr) {
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@ -23,7 +23,7 @@ u32 ShaderIR::DecodeVideo(NodeBlock& bb, u32 pc) {
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const Node op_a =
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GetVideoOperand(GetRegister(instr.gpr8), instr.video.is_byte_chunk_a, instr.video.signed_a,
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instr.video.type_a, instr.video.byte_height_a);
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const Node op_b = [&]() {
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const Node op_b = [this, instr] {
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if (instr.video.use_register_b) {
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return GetVideoOperand(GetRegister(instr.gpr20), instr.video.is_byte_chunk_b,
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instr.video.signed_b, instr.video.type_b,
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@ -46,9 +46,10 @@ u32 ShaderIR::DecodeWarp(NodeBlock& bb, u32 pc) {
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break;
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}
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case OpCode::Id::SHFL: {
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Node width = [this, instr] {
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Node mask = instr.shfl.is_mask_imm ? Immediate(static_cast<u32>(instr.shfl.mask_imm))
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: GetRegister(instr.gpr39);
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Node width = [&] {
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// Convert the obscure SHFL mask back into GL_NV_shader_thread_shuffle's width. This has
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// been done reversing Nvidia's math. It won't work on all cases due to SHFL having
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// different parameters that don't properly map to GLSL's interface, but it should work
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