Pica/VertexShader: Fix a bug in the bitfield definitions and add the "negate" field for swizzlers.
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26ade98411
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62c36a4ef0
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@ -65,26 +65,32 @@ static void ProcessShaderCode(VertexShaderState& state) {
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const Instruction& instr = *(const Instruction*)state.program_counter;
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const Instruction& instr = *(const Instruction*)state.program_counter;
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state.debug.max_offset = std::max<u32>(state.debug.max_offset, 1 + (state.program_counter - shader_memory));
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state.debug.max_offset = std::max<u32>(state.debug.max_offset, 1 + (state.program_counter - shader_memory));
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const float24* src1_ = (instr.common.src1 < 0x10) ? state.input_register_table[instr.common.src1]
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const float24* src1_ = (instr.common.src1 < 0x10) ? state.input_register_table[instr.common.src1.GetIndex()]
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: (instr.common.src1 < 0x20) ? &state.temporary_registers[instr.common.src1-0x10].x
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: (instr.common.src1 < 0x20) ? &state.temporary_registers[instr.common.src1.GetIndex()].x
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: (instr.common.src1 < 0x80) ? &shader_uniforms.f[instr.common.src1-0x20].x
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: (instr.common.src1 < 0x80) ? &shader_uniforms.f[instr.common.src1.GetIndex()].x
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: nullptr;
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: nullptr;
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const float24* src2_ = (instr.common.src2 < 0x10) ? state.input_register_table[instr.common.src2]
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const float24* src2_ = (instr.common.src2 < 0x10) ? state.input_register_table[instr.common.src2.GetIndex()]
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: &state.temporary_registers[instr.common.src2-0x10].x;
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: &state.temporary_registers[instr.common.src2.GetIndex()].x;
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// TODO: Unsure about the limit values
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float24* dest = (instr.common.dest < 0x08) ? state.output_register_table[4*instr.common.dest.GetIndex()]
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float24* dest = (instr.common.dest <= 0x1C) ? state.output_register_table[instr.common.dest]
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: (instr.common.dest < 0x10) ? nullptr
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: (instr.common.dest <= 0x3C) ? nullptr
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: (instr.common.dest < 0x20) ? &state.temporary_registers[instr.common.dest.GetIndex()][0]
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: (instr.common.dest <= 0x7C) ? &state.temporary_registers[(instr.common.dest-0x40)/4][instr.common.dest%4]
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: nullptr;
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: nullptr;
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const SwizzlePattern& swizzle = *(SwizzlePattern*)&swizzle_data[instr.common.operand_desc_id];
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const SwizzlePattern& swizzle = *(SwizzlePattern*)&swizzle_data[instr.common.operand_desc_id];
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const bool negate_src1 = swizzle.negate;
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const float24 src1[4] = {
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float24 src1[4] = {
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src1_[(int)swizzle.GetSelectorSrc1(0)],
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src1_[(int)swizzle.GetSelectorSrc1(0)],
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src1_[(int)swizzle.GetSelectorSrc1(1)],
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src1_[(int)swizzle.GetSelectorSrc1(1)],
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src1_[(int)swizzle.GetSelectorSrc1(2)],
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src1_[(int)swizzle.GetSelectorSrc1(2)],
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src1_[(int)swizzle.GetSelectorSrc1(3)],
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src1_[(int)swizzle.GetSelectorSrc1(3)],
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};
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};
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if (negate_src1) {
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src1[0] = src1[0] * float24::FromFloat32(-1);
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src1[1] = src1[1] * float24::FromFloat32(-1);
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src1[2] = src1[2] * float24::FromFloat32(-1);
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src1[3] = src1[3] * float24::FromFloat32(-1);
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}
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const float24 src2[4] = {
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const float24 src2[4] = {
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src2_[(int)swizzle.GetSelectorSrc2(0)],
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src2_[(int)swizzle.GetSelectorSrc2(0)],
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src2_[(int)swizzle.GetSelectorSrc2(1)],
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src2_[(int)swizzle.GetSelectorSrc2(1)],
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@ -117,9 +117,78 @@ union Instruction {
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// while "dest" addresses individual floats.
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// while "dest" addresses individual floats.
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union {
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union {
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BitField<0x00, 0x5, u32> operand_desc_id;
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BitField<0x00, 0x5, u32> operand_desc_id;
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BitField<0x07, 0x5, u32> src2;
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BitField<0x0c, 0x7, u32> src1;
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template<class BitFieldType>
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BitField<0x13, 0x7, u32> dest;
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struct SourceRegister : BitFieldType {
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enum RegisterType {
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Input,
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Temporary,
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FloatUniform
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};
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RegisterType GetRegisterType() const {
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if (BitFieldType::Value() < 0x10)
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return Input;
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else if (BitFieldType::Value() < 0x20)
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return Temporary;
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else
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return FloatUniform;
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}
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int GetIndex() const {
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if (GetRegisterType() == Input)
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return BitFieldType::Value();
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else if (GetRegisterType() == Temporary)
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return BitFieldType::Value() - 0x10;
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else if (GetRegisterType() == FloatUniform)
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return BitFieldType::Value() - 0x20;
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}
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std::string GetRegisterName() const {
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std::map<RegisterType, std::string> type = {
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{ Input, "i" },
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{ Temporary, "t" },
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{ FloatUniform, "f" },
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};
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return type[GetRegisterType()] + std::to_string(GetIndex());
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}
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};
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SourceRegister<BitField<0x07, 0x5, u32>> src2;
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SourceRegister<BitField<0x0c, 0x7, u32>> src1;
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struct : BitField<0x15, 0x5, u32>
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{
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enum RegisterType {
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Output,
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Temporary,
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Unknown
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};
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RegisterType GetRegisterType() const {
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if (Value() < 0x8)
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return Output;
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else if (Value() < 0x10)
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return Unknown;
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else
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return Temporary;
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}
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int GetIndex() const {
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if (GetRegisterType() == Output)
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return Value();
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else if (GetRegisterType() == Temporary)
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return Value() - 0x10;
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else
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return Value();
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}
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std::string GetRegisterName() const {
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std::map<RegisterType, std::string> type = {
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{ Output, "o" },
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{ Temporary, "t" },
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{ Unknown, "u" }
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};
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return type[GetRegisterType()] + std::to_string(GetIndex());
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}
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} dest;
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} common;
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} common;
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// Format used for flow control instructions ("if")
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// Format used for flow control instructions ("if")
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@ -128,6 +197,7 @@ union Instruction {
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BitField<0x0a, 0xc, u32> offset_words;
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BitField<0x0a, 0xc, u32> offset_words;
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} flow_control;
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} flow_control;
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};
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};
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static_assert(std::is_standard_layout<Instruction>::value, "Structure is not using standard layout!");
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union SwizzlePattern {
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union SwizzlePattern {
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u32 hex;
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u32 hex;
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@ -185,6 +255,8 @@ union SwizzlePattern {
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// Components of "dest" that should be written to: LSB=dest.w, MSB=dest.x
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// Components of "dest" that should be written to: LSB=dest.w, MSB=dest.x
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BitField< 0, 4, u32> dest_mask;
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BitField< 0, 4, u32> dest_mask;
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BitField< 4, 1, u32> negate; // negates src1
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BitField< 5, 2, Selector> src1_selector_3;
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BitField< 5, 2, Selector> src1_selector_3;
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BitField< 7, 2, Selector> src1_selector_2;
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BitField< 7, 2, Selector> src1_selector_2;
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BitField< 9, 2, Selector> src1_selector_1;
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BitField< 9, 2, Selector> src1_selector_1;
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