Merge pull request #11383 from FernandoS27/are-you-a-wabbit
Fix regressions that damaged compute indirect & use reinterpret for copies with different byteblocksizes
This commit is contained in:
commit
76bddd3673
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@ -161,7 +161,8 @@ enum class SpecialRegister : u64 {
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LOG_WARNING(Shader, "(STUBBED) SR_AFFINITY");
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LOG_WARNING(Shader, "(STUBBED) SR_AFFINITY");
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return ir.Imm32(0); // This is the default value hardware returns.
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return ir.Imm32(0); // This is the default value hardware returns.
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default:
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default:
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throw NotImplementedException("S2R special register {}", special_register);
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LOG_CRITICAL(Shader, "(STUBBED) Special register {}", special_register);
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return ir.Imm32(0); // This is the default value hardware returns.
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}
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}
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}
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}
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} // Anonymous namespace
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} // Anonymous namespace
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@ -14,6 +14,7 @@
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namespace Tegra {
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namespace Tegra {
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constexpr u32 MacroRegistersStart = 0xE00;
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constexpr u32 MacroRegistersStart = 0xE00;
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constexpr u32 ComputeInline = 0x6D;
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DmaPusher::DmaPusher(Core::System& system_, GPU& gpu_, MemoryManager& memory_manager_,
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DmaPusher::DmaPusher(Core::System& system_, GPU& gpu_, MemoryManager& memory_manager_,
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Control::ChannelState& channel_state_)
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Control::ChannelState& channel_state_)
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@ -83,12 +84,35 @@ bool DmaPusher::Step() {
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dma_state.dma_get, command_list_header.size * sizeof(u32));
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dma_state.dma_get, command_list_header.size * sizeof(u32));
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}
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}
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}
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}
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Core::Memory::GpuGuestMemory<Tegra::CommandHeader,
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const auto safe_process = [&] {
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Core::Memory::GuestMemoryFlags::UnsafeRead>
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Core::Memory::GpuGuestMemory<Tegra::CommandHeader,
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headers(memory_manager, dma_state.dma_get, command_list_header.size, &command_headers);
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Core::Memory::GuestMemoryFlags::SafeRead>
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ProcessCommands(headers);
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headers(memory_manager, dma_state.dma_get, command_list_header.size,
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&command_headers);
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ProcessCommands(headers);
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};
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const auto unsafe_process = [&] {
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Core::Memory::GpuGuestMemory<Tegra::CommandHeader,
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Core::Memory::GuestMemoryFlags::UnsafeRead>
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headers(memory_manager, dma_state.dma_get, command_list_header.size,
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&command_headers);
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ProcessCommands(headers);
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};
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if (Settings::IsGPULevelHigh()) {
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if (dma_state.method >= MacroRegistersStart) {
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unsafe_process();
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return true;
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}
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if (subchannel_type[dma_state.subchannel] == Engines::EngineTypes::KeplerCompute &&
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dma_state.method == ComputeInline) {
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unsafe_process();
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return true;
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}
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safe_process();
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return true;
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}
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unsafe_process();
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}
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}
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return true;
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return true;
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}
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}
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@ -130,8 +130,10 @@ public:
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void DispatchCalls();
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void DispatchCalls();
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void BindSubchannel(Engines::EngineInterface* engine, u32 subchannel_id) {
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void BindSubchannel(Engines::EngineInterface* engine, u32 subchannel_id,
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Engines::EngineTypes engine_type) {
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subchannels[subchannel_id] = engine;
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subchannels[subchannel_id] = engine;
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subchannel_type[subchannel_id] = engine_type;
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}
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}
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void BindRasterizer(VideoCore::RasterizerInterface* rasterizer);
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void BindRasterizer(VideoCore::RasterizerInterface* rasterizer);
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@ -170,6 +172,7 @@ private:
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const bool ib_enable{true}; ///< IB mode enabled
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const bool ib_enable{true}; ///< IB mode enabled
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std::array<Engines::EngineInterface*, max_subchannels> subchannels{};
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std::array<Engines::EngineInterface*, max_subchannels> subchannels{};
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std::array<Engines::EngineTypes, max_subchannels> subchannel_type;
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GPU& gpu;
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GPU& gpu;
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Core::System& system;
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Core::System& system;
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@ -11,6 +11,14 @@
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namespace Tegra::Engines {
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namespace Tegra::Engines {
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enum class EngineTypes : u32 {
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KeplerCompute,
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Maxwell3D,
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Fermi2D,
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MaxwellDMA,
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KeplerMemory,
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};
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class EngineInterface {
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class EngineInterface {
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public:
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public:
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virtual ~EngineInterface() = default;
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virtual ~EngineInterface() = default;
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@ -69,6 +69,14 @@ public:
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/// Binds a rasterizer to this engine.
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/// Binds a rasterizer to this engine.
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void BindRasterizer(VideoCore::RasterizerInterface* rasterizer);
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void BindRasterizer(VideoCore::RasterizerInterface* rasterizer);
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GPUVAddr ExecTargetAddress() const {
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return regs.dest.Address();
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}
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u32 GetUploadSize() const {
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return copy_size;
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}
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private:
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private:
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void ProcessData(std::span<const u8> read_buffer);
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void ProcessData(std::span<const u8> read_buffer);
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@ -43,16 +43,33 @@ void KeplerCompute::CallMethod(u32 method, u32 method_argument, bool is_last_cal
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switch (method) {
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switch (method) {
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case KEPLER_COMPUTE_REG_INDEX(exec_upload): {
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case KEPLER_COMPUTE_REG_INDEX(exec_upload): {
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UploadInfo info{.upload_address = upload_address,
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.exec_address = upload_state.ExecTargetAddress(),
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.copy_size = upload_state.GetUploadSize()};
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uploads.push_back(info);
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upload_state.ProcessExec(regs.exec_upload.linear != 0);
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upload_state.ProcessExec(regs.exec_upload.linear != 0);
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break;
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break;
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}
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}
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case KEPLER_COMPUTE_REG_INDEX(data_upload): {
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case KEPLER_COMPUTE_REG_INDEX(data_upload): {
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upload_address = current_dma_segment;
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upload_state.ProcessData(method_argument, is_last_call);
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upload_state.ProcessData(method_argument, is_last_call);
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break;
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break;
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}
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}
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case KEPLER_COMPUTE_REG_INDEX(launch):
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case KEPLER_COMPUTE_REG_INDEX(launch): {
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const GPUVAddr launch_desc_loc = regs.launch_desc_loc.Address();
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for (auto& data : uploads) {
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const GPUVAddr offset = data.exec_address - launch_desc_loc;
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if (offset / sizeof(u32) == LAUNCH_REG_INDEX(grid_dim_x) &&
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memory_manager.IsMemoryDirty(data.upload_address, data.copy_size)) {
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indirect_compute = {data.upload_address};
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}
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}
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uploads.clear();
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ProcessLaunch();
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ProcessLaunch();
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indirect_compute = std::nullopt;
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break;
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break;
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}
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default:
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default:
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break;
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break;
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}
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}
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@ -62,6 +79,7 @@ void KeplerCompute::CallMultiMethod(u32 method, const u32* base_start, u32 amoun
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u32 methods_pending) {
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u32 methods_pending) {
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switch (method) {
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switch (method) {
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case KEPLER_COMPUTE_REG_INDEX(data_upload):
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case KEPLER_COMPUTE_REG_INDEX(data_upload):
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upload_address = current_dma_segment;
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upload_state.ProcessData(base_start, amount);
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upload_state.ProcessData(base_start, amount);
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return;
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return;
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default:
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default:
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@ -5,6 +5,7 @@
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#include <array>
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#include <array>
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#include <cstddef>
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#include <cstddef>
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#include <optional>
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#include <vector>
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#include <vector>
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#include "common/bit_field.h"
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#include "common/bit_field.h"
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#include "common/common_funcs.h"
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#include "common/common_funcs.h"
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@ -36,6 +37,9 @@ namespace Tegra::Engines {
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#define KEPLER_COMPUTE_REG_INDEX(field_name) \
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#define KEPLER_COMPUTE_REG_INDEX(field_name) \
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(offsetof(Tegra::Engines::KeplerCompute::Regs, field_name) / sizeof(u32))
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(offsetof(Tegra::Engines::KeplerCompute::Regs, field_name) / sizeof(u32))
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#define LAUNCH_REG_INDEX(field_name) \
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(offsetof(Tegra::Engines::KeplerCompute::LaunchParams, field_name) / sizeof(u32))
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class KeplerCompute final : public EngineInterface {
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class KeplerCompute final : public EngineInterface {
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public:
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public:
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explicit KeplerCompute(Core::System& system, MemoryManager& memory_manager);
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explicit KeplerCompute(Core::System& system, MemoryManager& memory_manager);
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@ -201,6 +205,10 @@ public:
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void CallMultiMethod(u32 method, const u32* base_start, u32 amount,
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void CallMultiMethod(u32 method, const u32* base_start, u32 amount,
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u32 methods_pending) override;
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u32 methods_pending) override;
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std::optional<GPUVAddr> GetIndirectComputeAddress() const {
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return indirect_compute;
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}
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private:
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private:
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void ProcessLaunch();
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void ProcessLaunch();
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@ -216,6 +224,15 @@ private:
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MemoryManager& memory_manager;
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MemoryManager& memory_manager;
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VideoCore::RasterizerInterface* rasterizer = nullptr;
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VideoCore::RasterizerInterface* rasterizer = nullptr;
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Upload::State upload_state;
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Upload::State upload_state;
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GPUVAddr upload_address;
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struct UploadInfo {
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GPUVAddr upload_address;
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GPUVAddr exec_address;
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u32 copy_size;
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};
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std::vector<UploadInfo> uploads;
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std::optional<GPUVAddr> indirect_compute{};
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};
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};
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#define ASSERT_REG_POSITION(field_name, position) \
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#define ASSERT_REG_POSITION(field_name, position) \
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@ -34,19 +34,24 @@ void Puller::ProcessBindMethod(const MethodCall& method_call) {
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bound_engines[method_call.subchannel] = engine_id;
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bound_engines[method_call.subchannel] = engine_id;
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switch (engine_id) {
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switch (engine_id) {
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case EngineID::FERMI_TWOD_A:
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case EngineID::FERMI_TWOD_A:
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dma_pusher.BindSubchannel(channel_state.fermi_2d.get(), method_call.subchannel);
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dma_pusher.BindSubchannel(channel_state.fermi_2d.get(), method_call.subchannel,
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EngineTypes::Fermi2D);
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break;
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break;
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case EngineID::MAXWELL_B:
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case EngineID::MAXWELL_B:
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dma_pusher.BindSubchannel(channel_state.maxwell_3d.get(), method_call.subchannel);
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dma_pusher.BindSubchannel(channel_state.maxwell_3d.get(), method_call.subchannel,
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EngineTypes::Maxwell3D);
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break;
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break;
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case EngineID::KEPLER_COMPUTE_B:
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case EngineID::KEPLER_COMPUTE_B:
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dma_pusher.BindSubchannel(channel_state.kepler_compute.get(), method_call.subchannel);
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dma_pusher.BindSubchannel(channel_state.kepler_compute.get(), method_call.subchannel,
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EngineTypes::KeplerCompute);
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break;
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break;
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case EngineID::MAXWELL_DMA_COPY_A:
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case EngineID::MAXWELL_DMA_COPY_A:
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dma_pusher.BindSubchannel(channel_state.maxwell_dma.get(), method_call.subchannel);
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dma_pusher.BindSubchannel(channel_state.maxwell_dma.get(), method_call.subchannel,
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EngineTypes::MaxwellDMA);
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break;
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break;
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case EngineID::KEPLER_INLINE_TO_MEMORY_B:
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case EngineID::KEPLER_INLINE_TO_MEMORY_B:
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dma_pusher.BindSubchannel(channel_state.kepler_memory.get(), method_call.subchannel);
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dma_pusher.BindSubchannel(channel_state.kepler_memory.get(), method_call.subchannel,
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EngineTypes::KeplerMemory);
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break;
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break;
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default:
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default:
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UNIMPLEMENTED_MSG("Unimplemented engine {:04X}", engine_id);
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UNIMPLEMENTED_MSG("Unimplemented engine {:04X}", engine_id);
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@ -380,6 +380,17 @@ void RasterizerOpenGL::DispatchCompute() {
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pipeline->SetEngine(kepler_compute, gpu_memory);
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pipeline->SetEngine(kepler_compute, gpu_memory);
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pipeline->Configure();
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pipeline->Configure();
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const auto& qmd{kepler_compute->launch_description};
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const auto& qmd{kepler_compute->launch_description};
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auto indirect_address = kepler_compute->GetIndirectComputeAddress();
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if (indirect_address) {
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// DispatchIndirect
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static constexpr auto sync_info = VideoCommon::ObtainBufferSynchronize::FullSynchronize;
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const auto post_op = VideoCommon::ObtainBufferOperation::DiscardWrite;
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const auto [buffer, offset] =
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buffer_cache.ObtainBuffer(*indirect_address, 12, sync_info, post_op);
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glBindBuffer(GL_DISPATCH_INDIRECT_BUFFER, buffer->Handle());
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glDispatchComputeIndirect(static_cast<GLintptr>(offset));
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return;
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}
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glDispatchCompute(qmd.grid_dim_x, qmd.grid_dim_y, qmd.grid_dim_z);
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glDispatchCompute(qmd.grid_dim_x, qmd.grid_dim_y, qmd.grid_dim_z);
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++num_queued_commands;
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++num_queued_commands;
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has_written_global_memory |= pipeline->WritesGlobalMemory();
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has_written_global_memory |= pipeline->WritesGlobalMemory();
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@ -665,6 +665,19 @@ std::unique_ptr<GraphicsPipeline> PipelineCache::CreateGraphicsPipeline(
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std::move(modules), infos);
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std::move(modules), infos);
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} catch (const Shader::Exception& exception) {
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} catch (const Shader::Exception& exception) {
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auto hash = key.Hash();
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size_t env_index{0};
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for (size_t index = 0; index < Maxwell::MaxShaderProgram; ++index) {
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if (key.unique_hashes[index] == 0) {
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continue;
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}
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Shader::Environment& env{*envs[env_index]};
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++env_index;
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const u32 cfg_offset{static_cast<u32>(env.StartAddress() + sizeof(Shader::ProgramHeader))};
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Shader::Maxwell::Flow::CFG cfg(env, pools.flow_block, cfg_offset, index == 0);
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env.Dump(hash, key.unique_hashes[index]);
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}
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LOG_ERROR(Render_Vulkan, "{}", exception.what());
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LOG_ERROR(Render_Vulkan, "{}", exception.what());
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return nullptr;
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return nullptr;
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}
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}
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@ -463,6 +463,20 @@ void RasterizerVulkan::DispatchCompute() {
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pipeline->Configure(*kepler_compute, *gpu_memory, scheduler, buffer_cache, texture_cache);
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pipeline->Configure(*kepler_compute, *gpu_memory, scheduler, buffer_cache, texture_cache);
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|
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const auto& qmd{kepler_compute->launch_description};
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const auto& qmd{kepler_compute->launch_description};
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auto indirect_address = kepler_compute->GetIndirectComputeAddress();
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if (indirect_address) {
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// DispatchIndirect
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static constexpr auto sync_info = VideoCommon::ObtainBufferSynchronize::FullSynchronize;
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const auto post_op = VideoCommon::ObtainBufferOperation::DiscardWrite;
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const auto [buffer, offset] =
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buffer_cache.ObtainBuffer(*indirect_address, 12, sync_info, post_op);
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scheduler.RequestOutsideRenderPassOperationContext();
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scheduler.Record([indirect_buffer = buffer->Handle(),
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indirect_offset = offset](vk::CommandBuffer cmdbuf) {
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cmdbuf.DispatchIndirect(indirect_buffer, indirect_offset);
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});
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return;
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}
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const std::array<u32, 3> dim{qmd.grid_dim_x, qmd.grid_dim_y, qmd.grid_dim_z};
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const std::array<u32, 3> dim{qmd.grid_dim_x, qmd.grid_dim_y, qmd.grid_dim_z};
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scheduler.RequestOutsideRenderPassOperationContext();
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scheduler.RequestOutsideRenderPassOperationContext();
|
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scheduler.Record([dim](vk::CommandBuffer cmdbuf) { cmdbuf.Dispatch(dim[0], dim[1], dim[2]); });
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scheduler.Record([dim](vk::CommandBuffer cmdbuf) { cmdbuf.Dispatch(dim[0], dim[1], dim[2]); });
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||||||
|
|
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@ -92,6 +92,7 @@ void Load(VkDevice device, DeviceDispatch& dld) noexcept {
|
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X(vkCmdCopyImage);
|
X(vkCmdCopyImage);
|
||||||
X(vkCmdCopyImageToBuffer);
|
X(vkCmdCopyImageToBuffer);
|
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X(vkCmdDispatch);
|
X(vkCmdDispatch);
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X(vkCmdDispatchIndirect);
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X(vkCmdDraw);
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X(vkCmdDraw);
|
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X(vkCmdDrawIndexed);
|
X(vkCmdDrawIndexed);
|
||||||
X(vkCmdDrawIndirect);
|
X(vkCmdDrawIndirect);
|
||||||
|
|
|
@ -203,6 +203,7 @@ struct DeviceDispatch : InstanceDispatch {
|
||||||
PFN_vkCmdCopyImage vkCmdCopyImage{};
|
PFN_vkCmdCopyImage vkCmdCopyImage{};
|
||||||
PFN_vkCmdCopyImageToBuffer vkCmdCopyImageToBuffer{};
|
PFN_vkCmdCopyImageToBuffer vkCmdCopyImageToBuffer{};
|
||||||
PFN_vkCmdDispatch vkCmdDispatch{};
|
PFN_vkCmdDispatch vkCmdDispatch{};
|
||||||
|
PFN_vkCmdDispatchIndirect vkCmdDispatchIndirect{};
|
||||||
PFN_vkCmdDraw vkCmdDraw{};
|
PFN_vkCmdDraw vkCmdDraw{};
|
||||||
PFN_vkCmdDrawIndexed vkCmdDrawIndexed{};
|
PFN_vkCmdDrawIndexed vkCmdDrawIndexed{};
|
||||||
PFN_vkCmdDrawIndirect vkCmdDrawIndirect{};
|
PFN_vkCmdDrawIndirect vkCmdDrawIndirect{};
|
||||||
|
@ -1209,6 +1210,10 @@ public:
|
||||||
dld->vkCmdDispatch(handle, x, y, z);
|
dld->vkCmdDispatch(handle, x, y, z);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
void DispatchIndirect(VkBuffer indirect_buffer, VkDeviceSize offset) const noexcept {
|
||||||
|
dld->vkCmdDispatchIndirect(handle, indirect_buffer, offset);
|
||||||
|
}
|
||||||
|
|
||||||
void PipelineBarrier(VkPipelineStageFlags src_stage_mask, VkPipelineStageFlags dst_stage_mask,
|
void PipelineBarrier(VkPipelineStageFlags src_stage_mask, VkPipelineStageFlags dst_stage_mask,
|
||||||
VkDependencyFlags dependency_flags, Span<VkMemoryBarrier> memory_barriers,
|
VkDependencyFlags dependency_flags, Span<VkMemoryBarrier> memory_barriers,
|
||||||
Span<VkBufferMemoryBarrier> buffer_barriers,
|
Span<VkBufferMemoryBarrier> buffer_barriers,
|
||||||
|
|
Reference in New Issue